Dynamic SLC Region for TLC SSD Write Buffering
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Solution Overview
Problem
Current solid state drives (SSDs) with TLC NAND face inefficiencies in write performance and endurance due to the need for segregated SLC and TLC regions, leading to wasted capacity and increased costs, as the SLC region must be oversized for buffering and endurance, reducing available storage space and increasing power consumption.
Innovation Solution
Implementing a dynamic SLC region within SSDs that can revolve without adding new NAND capacity, allowing for efficient write buffering and endurance reduction, enabling more user-visible storage capacity and reducing NAND component qualification requirements, while utilizing existing overprovisioned capacity for SLC write buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a segregated SLC region is implemented for write buffering in TLC NAND SSDs, then write performance is improved, but storage capacity is reduced and costs increase
Solution Approach 1:
The patent implements a dynamic SLC region that can expand and contract based on write workload demands. During burst write operations, the SLC region dynamically expands to absorb writes at high speeds, then contracts during idle periods. This dynamic behavior allows the same physical space to serve both as high-performance buffer and as additional storage capacity, eliminating the need for permanently segregated SLC regions.
Solution Approach 2:
The patent changes the operational mode of NAND blocks between SLC and TLC modes based on workload conditions. By dynamically adjusting the cell programming parameters and voltage levels, existing TLC NAND blocks can temporarily operate in SLC mode for write buffering, then return to TLC mode for storage. This parameter switching allows the same hardware to provide both high-performance writing and high-capacity storage without physical segregation.
2Reliability
If an oversized SLC region is allocated for buffering and endurance, then write endurance is improved, but available storage space is reduced
Solution Approach 1:
The patent creates a dynamic SLC region that expands only when write operations are occurring, providing endurance protection during active writing, then contracts during idle periods to maximize storage capacity. This dynamic sizing ensures the SLC region is present only when needed for endurance and performance, not permanently occupying storage space.
Solution Approach 2:
The patent employs periodic expansion and contraction of the SLC region in sync with write workload patterns. The SLC buffer is activated periodically during write bursts to protect against wear, then deactivated during idle periods. This periodic action provides endurance protection only when necessary, allowing the same space to be used for storage during non-write periods.
3Speed
If SLC region capacity is increased for burst write buffering, then write speed is improved, but power consumption increases
Solution Approach 1:
The patent implements a dynamic SLC region that expands to high-speed buffer capacity only during burst write operations, then contracts to minimal size during idle periods. This dynamic scaling ensures high write speeds are available when needed, while power consumption is minimized during non-active periods since fewer blocks are maintained in the high-power SLC mode.
Solution Approach 2:
The patent uses periodic expansion and contraction of the SLC region synchronized with write workload demands. High-speed SLC buffering is activated periodically during write bursts, then deactivated during idle periods. This periodic activation provides high write speeds only when necessary, reducing overall power consumption compared to a permanently active SLC buffer.
Data Source
AI summary
Methods and apparatus related to cost optimized Single Level Cell (SLC) write buffering for Three Level Cell (TLC) Solid State Drives (SSDs) are described. In one embodiment, non-volatile memory includes a first region in a Single Level Cell (SLC) mode and a second region in a multiple level cell mode. A portion of the second region is moved from the multiple level cell mode to the SLC mode, without adding any new capacity to the non-volatile memory and without reducing any existing capacity from the non-volatile memory.