Dynamic SoC Clock Configuration via AXI Bus
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Solution Overview
Problem
Traditional clock frequency configuration in SoC systems is labor-intensive and costly, requiring devices to be powered off and on for frequency changes, as it relies on pre-defined settings from sample-at-reset pads, limiting flexibility and increasing manufacturing costs.
Innovation Solution
A dynamic clock configuration method using an Advanced eXtensible Interface (AXI) bus to change clock frequencies on-the-fly while the SoC is operational, allowing the central processing unit to configure clock domains without affecting other domains, utilizing a programmable AXI block to write new parameters to phase-locked loop circuits and clock division registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional sample-at-reset pads are used for clock frequency configuration, then the device can be manufactured with pre-defined frequency settings, but the device requires power cycling to change frequencies and cannot be reconfigured dynamically
Solution Approach 1:
The patent transforms the static clock configuration system into a dynamic one by introducing a programmable logic block that can be reconfigured at runtime. The AXI interface enables the processor to write new division factors to the clock circuit, allowing the system to adapt frequency settings dynamically without manufacturing changes or power cycling.
Solution Approach 2:
The invention changes the configurable parameters of the clock circuit from fixed hardware values (sampled at reset) to programmable values that can be modified during operation. By allowing the division factor parameter to be updated through the AXI bus, the system achieves flexible frequency reconfiguration while maintaining the same physical hardware.
2Ease of operation
If SAR pads are used to sample clock division factors at reset, then the clock frequency can be configured at power-up, but frequency changes require device power-off and re-power-up
Solution Approach 1:
The patent prepares the clock circuit for dynamic reconfiguration by integrating a programmable logic block and AXI interface during manufacturing. This preliminary setup enables future frequency changes to be performed quickly through software commands without requiring power cycling, thus eliminating the time loss associated with traditional reconfiguration methods.
Solution Approach 2:
The AXI interface acts as an intermediary between the processor and the clock circuit, enabling parameter updates without direct hardware changes. This mediator allows the system to transition from static to dynamic configuration by providing a communication channel for transmitting new division factors during operation.
3Adaptability or versatility
If dedicated SAR pads are provided for each clock circuit, then each clock domain can be independently configured, but the manufacturing cost of the SoC increases
Solution Approach 1:
The patent implements a universal programmable logic block that can serve multiple clock domains through the shared AXI interface. Instead of requiring dedicated hardware pads for each clock circuit, a single reconfigurable block can be programmed to configure different clock domains as needed, reducing the total number of physical components while maintaining independent configuration capability.
Solution Approach 2:
The invention merges the configuration functions of multiple clock circuits into a single programmable logic block. By combining what would traditionally require separate SAR pads into one reusable resource accessible via the AXI bus, the system reduces manufacturing complexity and cost while preserving the ability to independently configure each clock domain.
4Stability of the object's composition
If the clock division factors are fixed by hardware structure of SAR pads, then the device can be manufactured with stable frequency settings, but frequency changes outside the pre-defined set require device updates
Solution Approach 1:
The patent transforms the static division factor selection into a dynamic parameter that can be adjusted during operation. The programmable logic block receives division factors through the AXI interface and applies them to the clock circuit, enabling the system to adapt to new frequency requirements without manufacturing updates while maintaining stable operation.
Solution Approach 2:
The invention changes the division factor from a fixed hardware parameter to a programmable parameter that can be modified at runtime. This allows the system to expand its frequency range flexibility by loading new division factors through the AXI bus while maintaining the stability of the clock generation mechanism itself.
Data Source
AI summary
This disclosure describes a programmable clock configuration block disposed at the SoC system, which manages clock frequency change flow in a single clock domain on a SoC system to provide dynamic clock frequency configuration while the SoC system is in operation. The programmable clock configuration block is configured to interact with the CPU of the SoC system to configure or change parameters relating to the clock signal frequency while the CPU is in an inactive state.