Dynamic Stack Memory Allocation for Overflow-Safe IC Threads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits face challenges in managing limited memory resources and power consumption while maintaining system programming transparency, simplicity, and robustness, particularly due to non-consecutive memory allocation and stack overflow vulnerabilities.
Innovation Solution
A stack memory allocation controller that monitors processor activities to dynamically allocate and release memory blocks based on current needs, optimizing memory usage and power consumption by sharing blocks between threads and powering down unused memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more memory is allocated to each OS task stack to protect against stack overflow, then system robustness and security are improved, but overall memory availability decreases and memory size/cost increases
Solution Approach 1:
The patent implements dynamic stack memory allocation where the virtual memory translator continuously monitors processor activities and adjusts the mapping of pointers to memory blocks in real-time. This allows the system to allocate memory based on actual runtime needs rather than static worst-case estimates, resolving the contradiction between ensuring sufficient memory for robustness and maximizing memory availability for other uses.
Solution Approach 2:
The system changes the parameter of memory allocation from a fixed static value to a dynamic value that adapts based on monitored processor activities. The virtual memory translator modifies the mapping parameters responsive to actual stack usage patterns, allowing the system to maintain robustness while optimizing memory utilization.
2Ease of operation
If static memory allocation is used to simplify programming and ensure robustness, then system simplicity and reliability are improved, but memory utilization efficiency deteriorates
Solution Approach 1:
The virtual memory translator acts as an intermediary layer between the processor and physical memory blocks. It maintains programming simplicity by presenting a consistent virtual address space to developers while dynamically managing the actual physical memory allocation in the background. This mediator resolves the contradiction by handling the complexity of dynamic allocation transparently, keeping programming simple while optimizing memory utilization.
Solution Approach 2:
The system implements self-service through automatic monitoring and dynamic remapping of stack memory. The virtual memory translator autonomously monitors processor activities and adjusts memory allocation without requiring programmer intervention, maintaining programming simplicity while achieving efficient memory utilization through automated adaptation.
3Productivity
If consecutive memory allocation is used to improve memory utilization, then memory efficiency is improved, but power consumption increases due to inability to power off memory blocks
Solution Approach 1:
The patent segments memory into discrete controllable blocks and uses the virtual memory translator to manage allocation at the block level. This segmentation allows individual memory blocks to be independently powered on or off based on actual usage needs, resolving the contradiction between maintaining consecutive allocation for efficiency and enabling selective power-off for reduced power consumption.
Data Source
AI summary
An integrated circuit includes: a processor; a memory coupled to the processor; and a stack memory allocation controller coupled to the processor and the memory. The stack memory allocation controller has: a stack use manager configured to monitor activities of the processor. The stack memory allocation controller also has a virtual memory translator configured to: obtain a first mapping of pointers to a first sub-set of memory blocks of the memory assigned to a memory stack for a thread executed by the processor; and determine a second mapping of pointers to a second sub-set of memory blocks of the memory assigned to the memory stack and different than the first sub-set of memory blocks responsive to the monitored activities.