Dynamic Status Register Array for Concurrent Memory Polling
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Solution Overview
Problem
Conventional round robin polling methods for memory devices increase latency and power consumption due to idle waiting and bus transitions in systems with multiple memory devices.
Innovation Solution
Implementing a dynamic status registers array with concurrent polling via dedicated commands that assign operations to queue slots of a status bank, allowing simultaneous status reporting on a data bus, reducing idle time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If round robin polling is used to service multiple memory devices, then all devices can be serviced in a systematic manner, but latency and power consumption increase due to idle waiting and bus transitions
Solution Approach 1:
The patent implements dynamic status registers that can be concurrently accessed by multiple controllers simultaneously. The status registers are dynamically updated by memory devices to reflect their readiness state, allowing controllers to poll multiple devices at the same time rather than sequentially. This dynamic approach eliminates idle waiting time and reduces latency while maintaining systematic service of all memory devices.
2Productivity
If round robin polling is used to service multiple memory devices, then all devices can be serviced in a systematic manner, but power consumption increases due to idle waiting and bus transitions
Solution Approach 1:
The dynamic status register array allows multiple controllers to concurrently poll memory devices without sequential bus transitions. Controllers can simultaneously read status information from different memory devices, eliminating the need for controllers to remain in idle state between polls. This reduces power consumption by keeping controllers actively productive rather than in low-power idle modes, while still systematically servicing all memory devices.
3Loss of time
If concurrent polling is implemented with dynamic status registers, then latency and power consumption are reduced, but device complexity increases
Solution Approach 1:
The status register array is segmented into multiple independently addressable registers, each capable of being polled by different controllers simultaneously. This segmentation allows the system to achieve concurrent polling without requiring a monolithic complex status register. Each segment can be independently managed and updated by memory devices, reducing the complexity burden on any single register while enabling low-latency concurrent access across the system.
Data Source
AI summary
Methods, systems, and devices for dynamic status registers array are described. An apparatus may include one or more memory dice coupled with a data bus. The apparatus may further include a controller coupled with each of the memory dice via the data bus that is configured to transmit a first command associated with a first operation to a first memory die. The first command may assign an associated operation (e.g., the first operation) to a queue slot of a status bank that is associated with at least the first memory die. The controller may further transmit second command to the first memory die to request a status of the first operation. The controller may receive a status of the first operation via a channel (e.g., a first channel) of the data bus that is based on the assigned queue slot of the status bank.