Dynamic Switch Buffer Management for Large Network Switches

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Solution Overview

Problem

Existing buffer-management techniques, such as Virtual Output Queues (VOQs), face challenges in large switches with hundreds of input and output ports due to the quadratic growth of VOQs, leading to memory constraints and inefficiencies in handling high loads and fairness across data streams.

Innovation Solution

The dynamic switch buffer management (DSBM) system dynamically assigns data cells from host buffers to switch-ingress buffers based on occupancy, reducing the number of switch-ingress buffers needed and allowing for flexible assignment, thereby improving throughput, fairness, and reducing memory requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate VOQs are used for each output port, then head-of-line blocking is avoided, but the number of VOQs grows quadratically with the number of input and output ports

Engineering Contradiction:
Improvehead-of-line blocking avoidanceVSAvoidnumber of VOQs
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple output ports are merged into a single shared buffer at the switch ingress. Instead of having separate VOQs for each output port, the patent combines them into one buffer that serves multiple output ports, thereby reducing the total number of buffers from quadratic to linear scale while maintaining the ability to avoid head-of-line blocking through dynamic routing decisions

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared buffer at the switch ingress is designed to be universal, serving multiple output ports simultaneously. This multi-functional buffer can accommodate data cells destined for any output port, eliminating the need for separate dedicated buffers for each output port while maintaining flexible routing capabilities

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If separate VOQs are used for each output port, then data routing flexibility is maintained, but memory requirements increase significantly in large switches

Engineering Contradiction:
Improvedata routing flexibilityVSAvoidmemory requirements
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

Multiple output port queues are merged into a single shared buffer, reducing the total memory capacity required from the sum of individual queue sizes to just one buffer size. This consolidation maintains routing flexibility through software-controlled forwarding decisions rather than requiring separate physical queues for each output port

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If dynamic buffer assignment is implemented, then throughput improves at high loads, but control logic complexity increases

Engineering Contradiction:
Improveswitch throughputVSAvoidcontrol logic complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The buffer assignment is made dynamic rather than static. The system can adaptively assign data cells to different output ports based on real-time conditions such as buffer occupancy and output port availability. This dynamic approach improves throughput by optimizing buffer utilization under varying load conditions

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The control logic incorporates feedback mechanisms that monitor buffer occupancy levels and output port status. Based on this feedback, the system dynamically adjusts buffer assignments to prevent congestion and optimize data flow, thereby improving throughput while managing complexity through intelligent control rather than simple fixed routing

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8670454B2Dynamic assignment of data to switch-ingress buffers
Publication Date: 2014.03.11 ORACLE AMERICAN INC
  • US8670454B2 patent drawing
  • US8670454B2 patent drawing
  • US8670454B2 patent drawing

AI summary

Embodiments of a system that includes a switch and a buffer-management technique for storing signals in the system are described. In this system, data cells are dynamically assigned from a host buffer to at least a subset of switch-ingress buffers in the switch based at least in part on the occupancy of the switch-ingress buffers. This buffer-management technique may reduce the number of switch-ingress buffers relative to the number of input and output ports to the switch, which in turn may overcome the limitations posed by the amount of memory available on chips, thereby facilitating large switches.