Dynamic Switch Scaling in Buck Converters
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Solution Overview
Problem
Switched-mode power converters, such as buck converters, face inefficiencies due to switching and conduction losses in high-side and low-side switches, particularly in pulse-frequency modulation (PFM) mode, which affect power efficiency.
Innovation Solution
Dynamic switch size adjustment based on target output voltage, where the number of parallel-coupled transistors in high-side and low-side switches is selectively enabled or disabled to optimize the trade-off between switching and conduction losses, using a control logic block to determine the appropriate switch sizes for different voltage ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed switch size is used, then the circuit design is simple, but the power efficiency cannot be optimized across different operating conditions
Solution Approach 1:
The patent applies segmentation by dividing the switch into multiple parallel transistors that can be independently controlled. This allows the effective switch size to be segmented and adjusted in discrete steps based on operating conditions. The control logic selectively enables or disables specific transistor segments to match the required power level, achieving optimized efficiency without requiring a completely complex redesign.
2Loss of energy
If the switch size is dynamically adjusted based on operating conditions, then power efficiency is optimized, but the control system complexity increases
Solution Approach 1:
The patent applies parameter changes by adjusting the effective switch size parameter based on operating conditions. The control logic monitors load current and output voltage to determine the appropriate switch size configuration. By changing the physical parameter (switch size) in response to measured operating conditions, the system optimizes efficiency without requiring overly complex control algorithms.
Data Source
AI summary
Techniques for optimizing the trade-off between minimizing switching losses and minimizing conduction losses in a buck converter. In an aspect, each of a high-side switch and a low-side switch may be implemented as a plurality of parallel-coupled transistors, each transistor having an independently controllable gate voltage, allowing adjustment of the effective transistor size. In response to the target voltage of the buck converter corresponding to a relatively high voltage range, more high-side switch transistors and fewer low-side switch transistors may be selected. Similarly, in response to the target voltage corresponding to a relatively low voltage range, more low-side switch transistors and fewer high-side switch transistors may be selected. In an aspect, the techniques may be applied during a pulse-frequency modulation mode.