Dynamic SystemVerilog UDR Update for Mixed-Signal Verification
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Solution Overview
Problem
Current SystemVerilog mixed-signal verification techniques lack the flexibility to dynamically change resolution functions during simulation, requiring users to create multiple user-defined nettypes and recompile designs for different functionalities, such as debugging and performance optimization.
Innovation Solution
A method and system that allow users to dynamically update SystemVerilog User-Defined Resolution (UDR) functions during simulation, enabling the creation of a dynamic user-defined nettype without recompilation, by defining multiple UDRs in a separate package and selecting them at runtime using commands or tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple user-defined nettypes are created for different resolution functions, then functionality and versatility are improved, but device complexity and ease of manufacture deteriorate
Solution Approach 1:
The patent implements a universal nettype framework where a single user-defined nettype can support multiple resolution functions through dynamic selection mechanisms. Instead of creating separate nettypes for different functionalities, the system allows one nettype to accommodate multiple resolution functions (e.g., default, debug, performance-optimized versions) that can be switched during simulation based on runtime conditions.
Solution Approach 2:
The patent introduces dynamic resolution function selection that allows the resolution behavior to change during simulation without recompilation. The system enables runtime switching between different resolution functions associated with a nettype, allowing the same nettype to exhibit different behaviors (default, debug, optimized) depending on the simulation phase or conditions.
2Adaptability or versatility
If design recompilation is performed for different resolution functions, then adaptability is improved, but productivity and loss of time worsen
Solution Approach 1:
The patent implements dynamic resolution function switching that occurs during simulation runtime without requiring design recompilation. The system maintains multiple resolution functions in memory and allows selective activation based on runtime conditions, eliminating the need to recompile the design when changing resolution behaviors.
Solution Approach 2:
The patent performs preliminary preparation by compiling and storing multiple resolution functions during the initial elaboration phase. This preliminary action enables rapid switching between resolution functions during simulation without requiring recompilation, as all necessary resolution functions are pre-loaded and ready for dynamic selection.
3Adaptability or versatility
If multiple user-defined nettypes are maintained in a library, then adaptability is improved, but ease of operation and device complexity worsen
Solution Approach 1:
The patent creates a universal nettype interface that can invoke multiple resolution functions through a standardized mechanism. Instead of requiring users to manage multiple separate nettypes, the system provides a single nettype with a unified interface that internally supports multiple resolution functions, simplifying user operations while maintaining adaptability.
Solution Approach 2:
The patent introduces an intermediary mechanism (the nettype resolution function selection system) that mediates between the user's simple nettype reference and the complex multiple resolution functions. This intermediary handles the complexity of managing multiple resolution functions transparently, allowing users to operate with a simple interface while the system manages the complexity of switching between different resolution behaviors.
Data Source
AI summary
The present disclosure relates to a computer-implemented method for mixed signal design verification. Embodiments may include receiving, using a processor, an electronic circuit design and compiling and elaborating the electronic circuit design. Embodiments may also include simulating the electronic circuit design and updating, during the simulating, a System Verilog User-Defined Resolution function (“SV-UDR”) associated with the electronic circuit design.