Dynamic Systolic Array Networks for FPGA Parallelization
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Solution Overview
Problem
Existing technologies face challenges in implementing systolic arrays for general-purpose computing on Field-Programmable Gate Arrays (FPGAs) due to difficulties in programming and the inability to optimize core usage effectively.
Innovation Solution
A method and system that utilize dynamic systolic array networks to program FPGA multi-core processors, enabling FPGAs to run conventional programs written in languages like C, C++, Matlab, or Python without an operating system, through systolic parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If systolic arrays are implemented on FPGAs for general-purpose computing, then computing speed and parallelism are improved, but programming difficulty and implementation complexity increase significantly
Solution Approach 1:
The patent introduces an intermediary layer (systolic array interface and dataflow compiler) that translates high-level programming languages into systolic array operations. This mediator handles the complexity of mapping algorithms to hardware while maintaining ease of use for programmers, resolving the contradiction between high computing speed and programming difficulty.
Solution Approach 2:
The patent replaces traditional mechanical programming approaches (manual hardware configuration) with automated compilation and synthesis processes. The system automatically generates systolic array configurations from high-level code, eliminating the need for manual hardware design and significantly reducing implementation complexity while maintaining high performance.
2Productivity
If FPGAs are programmed using hardware description languages for systolic arrays, then processing performance is improved, but ease of programming deteriorates
Solution Approach 1:
The patent creates a virtual copy of the systolic array architecture in software form through a dataflow compiler and intermediate representation. This software model allows programmers to work with familiar high-level languages while the compiler translates these operations into optimized hardware configurations, maintaining processing performance while dramatically improving ease of programming.
Solution Approach 2:
The patent develops a universal programming interface that supports multiple high-level languages (C, C++, Matlab, Python) and automatically adapts them to systolic array execution. This universal layer allows the same programming interface to serve both traditional CPU programming and accelerated systolic array computing, improving ease of use without sacrificing performance.
3Adaptability or versatility
If conventional programming languages are used to program systolic arrays, then adaptability and versatility are improved, but optimization capability and performance deteriorate
Solution Approach 1:
The patent implements a dynamic compilation system that adapts the translation from high-level languages to systolic array operations based on the specific algorithm and data characteristics. The compiler dynamically optimizes dataflow patterns, memory access, and resource allocation during the compilation process, maintaining language flexibility while achieving performance close to hand-optimized hardware descriptions.
Solution Approach 2:
The patent incorporates feedback mechanisms in the compilation process where performance metrics from simulated or preliminary executions are used to refine the generated systolic array configuration. The system analyzes execution patterns and automatically adjusts dataflow optimizations, enabling high-level language programming to achieve optimized performance through iterative refinement.
Data Source
AI summary
An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.