Dynamic Tag Allocation for Clock Reconvergence Pessimism
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Solution Overview
Problem
Conventional static timing analysis tools produce overly pessimistic results due to exponential increase in tag size, leading to false failures and unnecessary resource consumption in digital circuit designs, especially in combinational logic circuits with multiple registers.
Innovation Solution
A critical slack based merging scheme is implemented during static timing analysis, where tags are consolidated by removing non-critical arrival times that exceed the maximal arrival time by a full clock delay spread, reducing tag size and improving analysis efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a breadth-first approach is used to maintain all worst-case arrival times in tags, then timing analysis completeness is improved, but tag size increases exponentially
Solution Approach 1:
The patent extracts and removes non-critical arrival times from tags by comparing each arrival time against the maximal arrival time at each node. Arrival times that do not contribute to the critical path (those less than the maximal arrival time minus full clock delay spread) are discarded, keeping only the essential timing information needed for accurate timing analysis.
Solution Approach 2:
The patent applies different treatment to different arrival times within tags based on their criticality. Critical arrival times (those that determine setup and hold timing slack) are maintained with full precision, while non-critical arrival times are removed. This local differentiation optimizes tag content to contain only necessary information.
2Measurement precision
If all worst-case arrival times are maintained in tags, then timing accuracy is improved, but false failures increase
Solution Approach 1:
The patent converts the potentially harmful effect of excessive timing conservatism into a benefit by systematically identifying and removing non-critical arrival times. The breadth-first approach that initially creates pessimism is transformed into a structured method for distinguishing critical from non-critical paths, eliminating false failures while preserving true timing violations.
3Reliability
If tag size increases to maintain all arrival times, then timing analysis thoroughness is improved, but resource consumption increases
Solution Approach 1:
The patent extracts unnecessary timing information from tags, removing arrival times that do not contribute to critical path analysis. This extraction process reduces the quantity of data that must be stored, processed, and propagated through the timing analysis engine, directly reducing computational and memory resources consumed.
4Measurement precision
If conventional timing analysis is used, then setup and hold timing slack is calculated, but overly pessimistic results are produced
Solution Approach 1:
The patent segments the set of all arrival times into critical and non-critical subsets. By dividing the timing information into these distinct categories and processing them differently (maintaining critical times, removing non-critical ones), the method achieves more precise timing slack calculation without the full complexity of maintaining all possible arrival times.
Data Source
AI summary
Electronic design automation tools may perform static timing analysis on an integrated circuit design. An integrated circuit design may have multiple nodes that can be traversed using a breadth-first search. To reduce the run-time of static timing analysis tools, tags recording arrival times associated with non-critical paths may have their consolidated in order to include only the critical timing information in the tag, thereby reducing the amount of data that is carried through to the analysis of the entire design. In a critical slack based merging method, a maximal arrival time associated with a circuit node may be compared to the remaining arrival times associated with the circuit node. Arrival times less than the maximal arrival time by an amount greater than a threshold amount may be deemed non-critical arrival times and may be removed from the tag for the circuit node.