Dynamic Target Refresh for Row Hammering in Semiconductor Memory
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Solution Overview
Problem
Semiconductor memory devices face data loss due to the row hammering phenomenon, where frequently accessed word lines can cause adjacent memory cells to lose data, necessitating an efficient target refresh operation to prevent data distortion.
Innovation Solution
A memory apparatus and method that includes a sampling circuit, storage circuit, arranging circuit, and selection control circuit to select and sequence addresses for a target refresh operation, using different algorithms to identify and prioritize addresses at high risk of data loss, thereby optimizing the target refresh process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single sampling method is used for target refresh operation, then the device complexity is low, but the reliability of data preservation is insufficient
Solution Approach 1:
The patent implements dynamic selection of sampling methods based on operational conditions. The sampling method selection circuit chooses between multiple sampling algorithms (first sampling method and second sampling method) depending on the current state of the memory system, allowing the refresh operation to adapt to different access patterns and row hammering scenarios, thereby improving data preservation reliability without permanently increasing device complexity
Solution Approach 2:
The patent changes the parameters of the sampling operation by using different sampling methods with different algorithms. The first sampling method and second sampling method have different parameters and characteristics, allowing the system to optimize for different conditions. This parameter variation enables better identification of addresses at high risk of data loss while maintaining manageable circuit complexity through structured selection
2Reliability
If multiple sampling methods are always used, then the reliability of data preservation is improved, but the device complexity increases
Solution Approach 1:
The system dynamically adjusts which sampling methods are active based on operational conditions rather than permanently implementing all possible sampling methods. The sampling method selection circuit enables the system to use multiple sampling methods when needed while falling back to simpler methods when conditions allow, thus improving reliability without permanently increasing device complexity
Solution Approach 2:
The patent segments the sampling operation into multiple independent sampling methods that can be selectively executed. Rather than implementing one complex unified sampling approach, the system divides the function into separate sampling circuits (first sampling circuit and second sampling circuit) that can be independently controlled and selected based on conditions, making the overall system more manageable
3Loss of information
If addresses are selected without considering access frequency, then the device complexity is low, but the loss of information increases due to row hammering
Solution Approach 1:
The patent implements feedback mechanisms where the sampling circuits monitor access patterns and identify addresses that are frequently accessed. This feedback information is used to prioritize these addresses for refresh operations, ensuring that rows at high risk of row hammering are protected. The feedback loop continuously adjusts which addresses are selected for refresh based on observed access behavior
Solution Approach 2:
The system performs preliminary identification of addresses at high risk of data loss through the sampling operation before actual data loss occurs. By proactively detecting frequently accessed rows and prioritizing them for refresh, the system prevents row hammering damage before it happens, rather than reacting after data loss is detected
Data Source
AI summary
A memory apparatus comprises: a sampling circuit for sampling an input address through a sampling method corresponding to a first selection signal among at least two sampling methods, a storage circuit for storing up to N number of addresses having different values among sampled addresses received from the sampling circuit, an arranging circuit for determining an output sequence of addresses stored in the storage circuit through an arranging method corresponding to a second selection signal among the two arranging methods, and setting, as a target address, an address outputted according to the output sequence, a selection control circuit for setting each of the first selection signal and the second selection signal based on a state of the storage circuit, and a refresh operation circuit for controlling a target refresh operation on a row of memory cells corresponding to the target address.