Dynamic Task Scheduling via Data Locality Tracking

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Solution Overview

Problem

In parallel computing systems, existing scheduling methods fail to efficiently distribute tasks across multiple processors due to non-uniform memory access times, leading to performance losses, especially when data is accessed repeatedly, as conventional heuristics lack data location information and require complex source code modifications.

Innovation Solution

A method that processes source code with parallel lambda functions to derive data location information, allowing tasks to be executed on processor cores associated with the memory units storing the required data, thereby optimizing memory access and reducing complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If conventional heuristics are used in the scheduler to distribute tasks, then tasks can be scheduled without complex source code modifications, but the scheduler lacks data location information leading to suboptimal memory access performance

Engineering Contradiction:
Improveease of schedulingVSAvoidmemory access performance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent introduces an intermediary component (the scheduling system with data location tracking) that bridges the gap between task execution and memory location information. The system automatically tracks and maintains data location information in memory without requiring source code modifications, thereby resolving the contradiction between ease of scheduling and memory access performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If explicit data location information is added to source code to influence scheduling, then memory access performance can be optimized, but the source code complexity increases and becomes harder to maintain

Engineering Contradiction:
Improvememory access performanceVSAvoidsource code complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system implements self-service by automatically tracking data location information through memory access patterns without requiring any explicit annotations or modifications to the source code. The scheduling system autonomously gathers and utilizes data location information, thereby optimizing memory access performance while keeping source code simple and maintainable.

Inventive Principle:
Principle #25Self-service

3Productivity

If tasks are mapped to remote processors, then load balancing can be improved, but memory access time increases significantly due to non-uniform memory access

Engineering Contradiction:
Improveload balancingVSAvoidmemory access time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements dynamic task scheduling that adapts to data location information in real-time. Instead of static load balancing assignments, the system dynamically adjusts task-to-processor mapping based on current data locations, thereby reducing memory access time while maintaining effective load distribution across processors.

Inventive Principle:
Principle #15Dynamics

4Adaptability or versatility

If data is loaded from remote memory, then tasks can execute on any processor, but system performance is significantly reduced

Engineering Contradiction:
Improveprocessor flexibilityVSAvoidsystem performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The system performs preliminary action by pre-loading or pre-positioning data in memory locations that are optimally accessible to the processors that will need them. By anticipating data access patterns and preparing data locations in advance, the system maintains processor flexibility while avoiding performance degradation from remote memory accesses.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9176716B2Method and apparatus for exploiting data locality in dynamic task scheduling
Publication Date: 2015.11.03 SIEMENS AG
  • US9176716B2 patent drawing
  • US9176716B2 patent drawing
  • US9176716B2 patent drawing

AI summary

A method for scheduling tasks to processor cores of a parallel computing system may include the steps of processing a source code which comprises at least one parallel lambda function having a function body called by a task and having a capture list specifying the data structures accessed in the function body of said parallel lambda function and used to derive data location information; executing the task calling said function body on the processor core which is associated to a memory unit of the parallel computing system where the data of the data structures specified by said capture list is stored, wherein the memory unit is selected or localized based on the derived data location information.