Dynamic Termination Resistor for Customizing Signal Eye on Shared Bus
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Solution Overview
Problem
In DDR3 fly-by nets, achieving suitable signal eye adjustments for all DRAM modules becomes increasingly difficult as data transmission rates rise, with traditional solutions either improving signal quality for the closest module at the expense of the last module or causing signal attenuation, making it hard to identify optimal control settings for all modules.
Innovation Solution
A system that includes a shared bus driver, dynamic termination resistor, and configuration logic to identify a target chip and adjust resistance values based on its location, optimizing signal quality specifically for the intended recipient chip by changing I/O impedance and slew rate, while potentially deactivating non-target chips to improve signal quality at the target chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the driver impedance is set lower and slew rate is set higher to accommodate more loads on a fly-by net, then the signal quality for DRAM modules closer to the driver is improved, but the signal attenuation increases causing degraded signal eye at the last DRAM module
Solution Approach 1:
The patent applies dynamics by making the termination resistance adjustable rather than fixed. The termination resistor can be dynamically changed based on which DRAM module is the target recipient of data, allowing the system to optimize signal quality for the specific target while accepting degraded signals at non-target modules. This dynamic adjustment resolves the contradiction by enabling high driver impedance (reducing attenuation) when targeting distant modules, while maintaining low impedance (improving signal quality) when targeting closer modules.
Solution Approach 2:
The patent changes the termination resistance parameter based on the target DRAM module location. By adjusting this parameter dynamically, the system can optimize the signal eye for the target module regardless of its position on the bus. This parameter change allows the system to overcome the traditional trade-off between signal quality and attenuation by adapting the termination resistance to match the specific communication requirements for each target module.
2Reliability
If electrical length is added between the driver and the first DRAM module to make the chain appear as a single load, then the signal quality at the first DRAM module is improved, but the extra trace length causes more attenuation for the last DRAM module
Solution Approach 1:
The patent uses dynamic termination resistance adjustment to compensate for varying trace lengths without actually adding electrical length. By adjusting the termination resistance based on the target module's position, the system can optimize signal quality for each target regardless of its distance from the driver, eliminating the need to add electrical length to accommodate multiple loads.
3Adaptability or versatility
If traditional control settings are used to support all DRAM modules on the fly-by net, then all modules can potentially receive signals, but suitable control settings become difficult to identify as data transmission rates increase
Solution Approach 1:
The patent applies local quality by optimizing control settings specifically for the target DRAM module rather than attempting to optimize for all modules simultaneously. The termination resistance and other control parameters are adjusted locally based on the target module's position and requirements. This approach simplifies the identification of suitable control settings because the system only needs to optimize for one target at a time, rather than finding a compromise setting that works for all modules.
Solution Approach 2:
The patent makes the control settings dynamic by adjusting them based on the identified target module. This dynamic adaptation allows the system to maintain high performance at increasing data rates by optimizing parameters for each specific communication transaction, rather than using static settings that must accommodate all possible targets.
Data Source
AI summary
The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.