Dynamic Test Sequence for Integrated Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated circuit testing methods are inefficient due to a fixed test sequence, leading to delayed identification of failing test items and wastage of time on non-failing items, and may result in wrongful passing of failed dies when skipping certain test items.
Innovation Solution
A dynamic adjustment of test sequences based on fail probability algorithms, such as Most Frequently Failed (MFF) and Temporal Frequently Failed (TFF), to prioritize test items that are more likely to fail, ensuring that these are tested earlier in the sequence, and incorporating temperature and stress monitoring to adjust the sequence accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a fixed test sequence is used for all dies, then the testing process is simple and consistent, but the time to identify failed test items is delayed and testing efficiency is reduced
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed test sequence to a dynamic test sequence that adapts based on real-time test results. The system monitors whether test items are passing or failing and adjusts the sequence accordingly, moving failing items to the front and skipping passing items, thereby optimizing testing efficiency while maintaining operational simplicity through automated adaptation.
2Reliability
If test items are executed in a fixed sequence die-by-die, then all test items are systematically covered, but time is wasted on non-failing items and failure identification is delayed
Solution Approach 1:
The patent applies preliminary action by analyzing test results from previously tested dies before proceeding to the next die. The system uses this historical data to predict which test items are likely to fail and prioritizes them in the test sequence, thereby identifying failures earlier without compromising comprehensive test coverage.
Solution Approach 2:
The patent implements feedback mechanisms where test results from each die are fed back into the system to dynamically adjust the test sequence for subsequent dies. This feedback loop enables the system to learn from previous failures and optimize the testing order, reducing time to identify failures while maintaining reliable test coverage.
3Loss of energy
If test items are skipped based on historical data, then test cost is reduced, but failed dies may wrongfully pass the test
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the test sequence based on real-time and historical test data. The system changes the order and selection of test items based on predicted failure probabilities, allocating testing resources more efficiently while maintaining test accuracy through continuous adaptation rather than static skipping.
4Productivity
If the most recently failed test item is moved to the top of the sequence, then the next die testing starts from the failure point, but test items that seldom fail may be tested repeatedly
Solution Approach 1:
The patent applies parameter changes by using failure probability as a dynamic parameter to sort test items. Instead of simply moving the most recent failure to the top, the system ranks all test items based on their historical failure rates and adjusts the sequence accordingly, reducing repeated testing of stable items while maintaining focus on problematic areas.
Data Source
AI summary
A method includes testing a first device and a second device identical to each other and comprising integrated circuits. The testing of the first device is performed according to a first test sequence of the first device, wherein the first test sequence includes a plurality of ordered test items, and wherein the first test sequence includes a test item. A test priority of the test item is calculated based on a frequency of fails of the test item in the testing of a plurality of devices having an identical structure as the first device. The first test sequence is then adjusted to generate a second test sequence in response to the test priority of the test item, wherein the second test sequence is different from the first test sequence. The second device is tested according to the second test sequence.