Dynamic Threshold Voltage Bins for Memory Cell Reliability
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Solution Overview
Problem
Existing memory sub-systems face increased bit error rates due to temporal voltage shift caused by slow charge loss in memory cells, which current strategies fail to adequately address, leading to inefficient error handling and performance losses.
Innovation Solution
Implementing a memory sub-system that tracks and adjusts threshold voltage offset bins based on program-erase cycles and temperature, grouping memory cells into block families to apply appropriate voltage offsets for read operations, thereby reducing bit error rates and preserving processing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are used for data storage, then data can be stored, but temporal voltage shift occurs due to slow charge loss leading to increased bit error rates
Solution Approach 1:
The patent implements dynamic adjustment of read threshold voltages based on the age of data in memory cells. The system transitions from static threshold voltages to dynamic thresholds that change over time, compensating for temporal voltage shift. This allows the read threshold to adapt to the degradation characteristics of memory cells, maintaining accurate data retrieval despite charge loss over time.
Solution Approach 2:
The patent changes the parameter of read threshold voltage based on data age and program-erase cycle counts. By modifying this critical parameter dynamically, the system compensates for temporal voltage shift and maintains reliable data reading. The threshold voltage is adjusted according to observed degradation patterns, transforming a static parameter into a dynamic one that adapts to memory cell conditions.
2Reliability
If current error handling strategies are used, then some error protection is provided, but performance is lost due to inefficient processing
Solution Approach 1:
The patent applies preliminary action by proactively adjusting read thresholds based on predicted temporal voltage shift before errors occur. Instead of reacting to errors after they manifest, the system pre-adjusts thresholds based on data age and degradation models, preventing errors before they impact performance. This proactive approach eliminates the need for complex post-error correction procedures.
Solution Approach 2:
The memory sub-system performs self-service by automatically tracking and compensating for temporal voltage shift without external intervention. The system monitors its own degradation characteristics and self-adjusts read thresholds, eliminating the need for complex external error handling mechanisms and preserving processing performance.
3Reliability
If multiple threshold voltage offset bins are used, then bit error rates are reduced, but device complexity increases
Solution Approach 1:
The patent segments the threshold voltage adjustment into discrete bins based on data age and program-erase cycle counts. This segmentation allows the system to manage complexity by organizing continuous degradation into manageable categories, each with its own optimized read threshold. The segmentation principle reduces complexity compared to continuous adjustment while maintaining effective error protection.
Data Source
AI summary
A system includes a memory device having a plurality of dice and A processing device to perform operations, including determining a representative number of program-erase cycles performed across the plurality of dice. The operations further include tracking the representative number of program-erase cycles over time. The operations further include, in response to the representative number of program-erase cycles satisfying a first threshold criterion, adding an additional threshold voltage offset bin to a plurality of threshold voltage offset bins for the memory device, wherein each of the plurality of threshold voltage offset bins comprises a corresponding window of time after program of data to the memory device.