Dynamic Timestamping Method Selection in Network Devices

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Solution Overview

Problem

Current clock synchronization protocols in network devices face challenges with one-step timestamping, which increases hardware requirements and power consumption, and two-step timestamping, which introduces latency and synchronization errors due to increased overhead and implementation complexity.

Innovation Solution

A network device is configured to dynamically select between one-step and two-step timestamping methods based on protocol requirements, using a processor to generate control headers that indicate the timestamping method, allowing for on-the-fly timestamping or storage and subsequent transmission of timing information, thereby optimizing hardware usage and reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If one-step timestamping is used to embed transmit timestamp in timing packet, then clock synchronization accuracy is improved, but hardware requirements and power consumption increase

Engineering Contradiction:
Improveclock synchronization accuracyVSAvoidhardware requirements
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements dynamic timestamping mode selection where the network device can switch between one-step and two-step timestamping methods based on packet type and protocol requirements. The control header includes a timestamping mode indicator field that dynamically specifies which method to use, allowing the system to optimize between accuracy and hardware complexity on a per-packet basis rather than requiring fixed high-capability hardware for all packets

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies different timestamping methods to different packet types locally. One-step timestamping is used only for packets where high precision is critical, while two-step timestamping is used for other packets. This localized application of quality ensures that hardware complexity is only elevated where measurement precision is actually required, rather than uniformly across all network traffic

Inventive Principle:
Principle #3Local quality

2Device complexity

If two-step timestamping is used to transmit timestamp in follow-up packet, then hardware requirements are reduced, but latency increases

Engineering Contradiction:
Improvehardware requirementsVSAvoidlatency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The system dynamically selects between one-step and two-step timestamping based on the timestamping mode indicator in the control header. For time-sensitive packets, one-step mode is selected to minimize latency, while for less time-critical traffic, two-step mode is used to reduce hardware complexity. This dynamic selection allows the system to optimize latency performance only when necessary rather than incurring latency penalties for all packets

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Different latency characteristics are applied locally to different packet types through the dynamic mode selection. Packets requiring low latency receive one-step timestamping treatment, while other packets use two-step timestamping. This ensures that latency is minimized only where it matters for specific packet types rather than uniformly across all traffic

Inventive Principle:
Principle #3Local quality

3Measurement precision

If one-step timestamping is implemented to embed timestamp on-the-fly, then synchronization accuracy is improved, but power consumption increases

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic power management through mode selection. The network device transitions between one-step and two-step timestamping modes based on traffic characteristics, allowing the system to consume higher power only when one-step timestamping is actually needed for accuracy, rather than maintaining high power consumption continuously. The control header's mode indicator enables this flexible power usage pattern

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

High power consumption associated with one-step timestamping is applied only locally to specific packet types that require high synchronization accuracy. The majority of packets can be handled with lower power consumption using two-step timestamping. This localized application of power-intensive processing ensures that energy is consumed only where it provides measurable benefit

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240430030A1Dynamic one-step/two-step timestamping per packet in network devices
Publication Date: 2024.12.26 MARVELL ISRAEL (M L S L) LTD
  • US20240430030A1 patent drawing
  • US20240430030A1 patent drawing
  • US20240430030A1 patent drawing

AI summary

A processor of a network device determines a timestamping method for communicating timing information corresponding to transmission of a timing message to another network device. The timestamping method is selected from a set of multiple timestamping methods that the network device is configured to perform, including: i) a one-step timestamping method, and ii) a two-step timestamping method. The processor generates a control header corresponding to the timing message, which includes a first field and a second field, the second field indicating a type of information within the first field. The first field indicates the timestamping method. The processor transfers the timing message to timestamping circuitry; and transfers the control header to the timestamping circuitry to indicate to the timestamping circuitry the timestamping method to be performed by the timestamping circuitry in connection with transmitting the timing message to the other network device.