Dynamic Trim Method for Non-Volatile Memory Yield
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Solution Overview
Problem
Manufacturing yield of memory circuits is hindered by rigid pre-determined margin levels that fail to account for process variations, leading to discarding otherwise functional devices during wafer sort and final testing.
Innovation Solution
Implementing a dynamic trimming method that determines individual memory device margin levels based on actual test results, allowing for optimized margin levels to cope with process variations and improve yield by sampling a portion of devices and using statistical analysis to set appropriate threshold levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If rigid pre-determined margin levels are used for wafer sort and final testing, then testing efficiency is maintained, but manufacturing yield decreases due to discarding functional devices that do not conform to fixed thresholds
Solution Approach 1:
The patent implements dynamic margin levels that automatically adjust based on measured device characteristics. Instead of using fixed predetermined thresholds, the system calculates individual margin levels for each memory device based on its actual performance metrics during testing, allowing the testing process to adapt to process variations and improve yield without requiring complex manual intervention
Solution Approach 2:
The system changes the testing parameters dynamically by calculating individual margin levels based on measured device characteristics such as program and erase speeds. The margin levels are adjusted according to the actual performance of each device, transforming static testing criteria into adaptive parameters that optimize yield while maintaining automated testing efficiency
2Productivity
If individual memory devices are tested and trimmed with customized margin levels, then manufacturing yield improves, but testing time and process complexity increase
Solution Approach 1:
The patent performs preliminary measurements of key device characteristics during initial testing, such as program and erase speeds. These measurements are used to calculate customized margin levels before final testing, allowing the system to prepare individualized testing criteria in advance and reduce overall testing time while improving yield
Solution Approach 2:
The system uses feedback from initial device measurements to adjust testing parameters. Measured characteristics such as program and erase speeds are fed back into the system to calculate appropriate margin levels, creating an iterative process that optimizes testing efficiency and yield without requiring excessive time for repeated measurements
3Ease of manufacture
If predetermined margin levels are used, then manufacturing process is simple, but process variations cause functional devices to be discarded
Solution Approach 1:
The patent applies local quality by tailoring margin levels to individual device characteristics rather than using uniform predetermined thresholds. Each memory device receives customized margin levels based on its specific performance metrics, allowing process variations in different regions and devices to be accommodated while maintaining simple automated manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases manufacturing yield by reducing unnecessary waste, optimizing margin levels for each die, and enabling the use of cheaper, more varied processes, thereby lowering costs and improving product quality.
Implementation Method 1
The nitride layer 51 is electrically isolated by surrounding oxide including an oxide layer 53 and a gate oxide layer 60. When the nitride layer 51 is charged, the charge shifts the MOSFET threshold voltage so that, with the same control gate voltage, current does not flow.
Implementation Method 2
Charging the nitride layer 51 is generally accomplished by grounding the source terminal, biasing the drain terminal, and placing sufficient voltage on the control gate 52 such that charge tunnels through the oxide 60 to the nitride layer 51. This is typically called channel-hot-electron (CHE) programming.
Implementation Method 3
Alternatively, SONOS devices can also be programmed with a sufficient gate-to-substrate voltage. This mechanism is known as 'Fowler-Nordheim' (FN) Tunneling.
Implementation Method 4
In the case of n-type SONOS, charges in the nitride layer 51 can also be cleared by a negatively biased control gate 52 and a positively biased source/drain. This mechanism is known as 'Hot Hole Band-to-Band Tunneling'.
Data Source
AI summary
A dynamic trim method includes testing a selected number of cells on a die with predetermined testing margins. Data from this testing is used to determine dynamic reference margins for improving yield. Advantageously, yield is improved by allowing functioning fast or slow units to pass wafer sort by applying the dynamic reference margins for varying processes.