Dynamic Verify Level for Memory Cell Programming Accuracy
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Solution Overview
Problem
In non-volatile memory devices, accurately programming the threshold voltage of select gate transistors and memory cells is challenging due to program disturb issues, where faster-programming transistors continue to increase in voltage beyond the desired level, widening the threshold voltage distribution.
Innovation Solution
Implementing a dynamic verify level that gradually increases during the programming operation, allowing faster-programming transistors to lock out at a lower voltage than slower-programming transistors, thereby bringing their threshold voltages to a common level and optimizing the initial and incremental verify levels to achieve a narrower threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a fixed verify level is used during programming, then the programming process is simple and fast, but faster-programming transistors continue to increase in voltage beyond the desired level, widening the threshold voltage distribution
Solution Approach 1:
The patent applies the dynamics principle by transitioning from a fixed verify level to a dynamic verify level that changes during the programming process. The verify level is initially set at a first level to allow fast programming, then switched to a second level (higher than the first) when certain transistors reach the second verify level, preventing over-programming and narrowing the threshold voltage distribution. This dynamic adjustment resolves the contradiction by making the programming process adaptive rather than static.
Solution Approach 2:
The patent implements parameter changes by modifying the verify level parameter during the programming operation. The verify level is changed from a first level to a second level based on the programming progress and transistor characteristics. This parameter change allows the system to accommodate both fast and slow programming transistors, achieving narrow threshold voltage distribution without requiring a completely complex new programming architecture.
2Reliability
If program pulses are continuously applied to all transistors, then all transistors can be programmed, but faster-programming transistors experience program disturb and their threshold voltage continues to increase past the desired level
Solution Approach 1:
The patent applies preliminary anti-action by implementing a lockout mechanism that prevents program pulses from being applied to transistors that have already reached the desired threshold voltage level. When a transistor's threshold voltage reaches the second verify level, it is locked out from receiving further program pulses, thereby preventing program disturb and threshold voltage over-increase. This preliminary protective action resolves the contradiction by stopping the harmful effect before it occurs.
Solution Approach 2:
The patent implements feedback by continuously monitoring the threshold voltage of transistors during programming and using this information to control the application of program pulses. The verify operation detects when transistors have reached the second verify level, and this feedback information is used to lock out those transistors from further programming. This feedback mechanism ensures programming accuracy while preventing program disturb in already-programmed transistors.
Data Source
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Figure 2B~2C
AI summary
Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage (Vv) which increases from an initial level (Vvinit) to a final level (Vvmx) during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial (Vvinit) and final (Vvmx) verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage (Vv) can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration.