Dynamic Verify Voltage Adjustment for Non-Volatile Memory Reliability
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Solution Overview
Problem
Non-volatile memory devices face challenges in maintaining accurate threshold voltage states due to variations in read operations, particularly caused by the coupling of word lines, which affect data retention and lead to issues like fail bit counts and data degradation over time.
Innovation Solution
A memory apparatus and method that include a control circuit capable of detecting use characteristics to adjust verify voltages by offsets, ensuring accurate programming and read operations, thereby minimizing fail bit counts and improving data retention by optimizing verify levels for power-on and power-off states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed verify voltage is used for programming operations, then the programming process is simple and fast, but data retention deteriorates due to word line coupling variations and fail bit counts increase
Solution Approach 1:
The patent implements dynamic verify voltage adjustment by detecting word line coupling effects during programming operations and adapting the verify voltage level accordingly. The control circuit monitors programming status and modifies verify voltage in real-time to compensate for coupling variations, transforming a static voltage system into a dynamic one that adapts to changing conditions, thereby improving data retention without excessive complexity
Solution Approach 2:
The patent changes the verify voltage parameter based on detected use characteristics and coupling effects. By adjusting the voltage level dynamically during programming operations, the system optimizes the verify threshold to match actual device conditions, reducing fail bit counts and improving data retention while maintaining manageable system complexity through parameter adaptation
2Reliability
If verify level offsets are adjusted to minimize fail bit counts, then data retention improves, but programming time increases due to additional verification steps
Solution Approach 1:
The patent applies partial adjustment of verify levels rather than complete re-verification. By using verify level offsets that compensate for coupling effects without requiring full re-programming verification, the system achieves improved data retention while minimizing additional programming time. The offset adjustment provides sufficient correction without excessive verification steps
Solution Approach 2:
The patent replaces time-consuming mechanical re-verification processes with electronic offset adjustments. Instead of physically re-performing verification steps, the system uses control circuitry to electronically adjust verify voltage levels based on detected conditions, substituting a time-intensive process with a faster electronic compensation mechanism that maintains reliability
3Reliability
If verify levels are optimized for power-on state, then data retention during power-on improves, but performance deteriorates in power-off state and vice versa
Solution Approach 1:
The patent creates a universal verify voltage adjustment mechanism that functions effectively in both power-on and power-off states. The control circuit detects use characteristics regardless of power state and applies appropriate verify level offsets, making the system adaptable to multiple operating conditions. This multi-functional approach allows the same circuitry to optimize data retention in both power states without requiring separate optimization mechanisms
Data Source
AI summary
A memory apparatus and method of operation are provided. The apparatus includes a plurality of memory cells. Each of the plurality of memory cells is connected to one of a plurality of word lines and is arranged in one of a plurality of blocks. Each of the plurality of memory cells is configured to retain a threshold voltage corresponding to one of a plurality of data states. A control circuit is coupled to the plurality of word lines and is configured to detect at least one use characteristic of the memory apparatus. The control circuit adjusts a verify voltage level by one of a plurality of verify level offsets based on the at least one use characteristic that is detected. The verify voltage level is applied to the one of the plurality of word lines selected for programming following an application of a program voltage during a program operation.