Dynamic Via Pillar Selection for Electromigration Mitigation
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Solution Overview
Problem
Electromigration (EM) in integrated circuits causes metal atom transport and potential open-circuit failures due to increasing current densities, leading to inefficient resource allocation and poor Power Performance Area (PPA) results when attempting to prevent EM through over-design.
Innovation Solution
The method involves swapping a minimum EM via pillar with an appropriate via pillar based on toggle rate and loading capacitance to alleviate EM phenomena, optimizing routing resources and improving PPA without increasing pin density, by using EM checking and optimization processes during the integrated circuit fabrication flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If over-design cell by putting much BEOL resource for cell EM signoff, then EM violations are prevented, but routing resources are wasted and PPA results deteriorate
Solution Approach 1:
The patent changes the parameter of via pillar configuration from a fixed over-designed approach to a dynamic selection based on actual toggle rate and loading capacitance. By calculating EM risk for different via pillar types and selecting the minimum sufficient configuration, the patent prevents EM violations while avoiding excessive resource allocation, thus improving PPA results.
Solution Approach 2:
Instead of applying excessive EM prevention measures uniformly to all cells, the patent applies partial action by selectively optimizing via pillar configuration only for cells where EM risk is actually present. The patent calculates EM risk for each cell and applies the minimum necessary via pillar enhancement, avoiding unnecessary resource consumption in cells with low EM risk.
2Reliability
If increase via pillar size to prevent EM, then EM resistance is improved, but routing resources are consumed and pin density increases
Solution Approach 1:
The patent changes the via pillar configuration parameter based on calculated EM risk, toggle rate, and loading capacitance. By selecting from multiple via pillar types (e.g., 1x1, 2x1, 2x2) rather than uniformly using the largest size, the patent achieves adequate EM resistance while minimizing routing resource consumption and pin density increase.
Solution Approach 2:
The patent applies via pillar enhancement partially - only to the extent necessary for each cell's actual EM risk. By calculating the minimum sufficient via pillar configuration for each cell based on its specific electrical characteristics, the patent avoids excessive via pillar sizing that would waste routing resources and increase pin density.
3Productivity
If use minimum EM via pillar, then routing resources are conserved, but EM violations may occur
Solution Approach 1:
The patent introduces feedback by calculating EM risk for each cell based on its actual toggle rate and loading capacitance, then using this feedback to select the appropriate via pillar configuration. This closed-loop approach ensures that the minimum sufficient via pillar is selected for each cell, preventing EM violations while optimizing routing resource efficiency.
Solution Approach 2:
The patent dynamically changes the via pillar configuration parameter based on calculated EM risk. By adjusting the via pillar size and type according to each cell's specific electrical characteristics rather than using a fixed minimum or maximum size, the patent achieves both EM violation prevention and routing resource efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces EM violations while conserving routing resources, enhancing the Power Performance Area (PPA) results by selecting the optimal via pillar configuration based on actual routing conditions and toggle rates.
Implementation Method 1
Electromigration (EM) is the transport of metal atoms when an electric current flows through a metallic structure in an integrated circuit (IC)
Data Source
AI summary
A method of forming an integrated device includes: providing a first via pillar file specifying a first via pillar; providing a second via pillar file specifying a second via pillar; arranging, by a processor, the first via pillar to electrically connect to a circuit cell in a first circuit; arranging an interconnecting path for electrical connection of the first via pillar to another circuit cell in the first circuit; arranging, by the processor, the second via pillar to replace the first via pillar when the first via pillar induces an electromigration (EM) phenomenon; re-routing the interconnecting path with replacement of the first via pillar to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.