Dynamic Video Stream Caching for Encoder Synchronization
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Solution Overview
Problem
Current systems face challenges in efficiently processing video streams due to synchronization issues between display engines and encoders, leading to increased latency and cache thrashing, which can result in dropped frames and higher latency.
Innovation Solution
A dynamic caching system that uses a threshold engine to determine when to write blended and composited pixels to a shared cache or memory based on the distance between pixel rows processed by the display engine and coding unit rows processed by the encoder, ensuring that the encoder does not get out of sync and reducing the likelihood of cache eviction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the display engine writes blended pixels to a shared cache, then memory access speed is improved, but cache thrashing occurs and encoder synchronization is disrupted
Solution Approach 1:
The patent implements dynamic caching by making the cache write operation conditional rather than static. The display engine dynamically determines whether to write to cache based on real-time synchronization status between the pixel row processor and encoder. When the encoder is ahead or synchronized, writes proceed to cache; when the encoder falls behind, writes are redirected to memory. This dynamic adaptation resolves the contradiction by adjusting cache usage behavior based on system state.
Solution Approach 2:
The system employs feedback mechanisms where the display engine continuously monitors the synchronization status between pixel processing and encoding operations. This feedback loop allows the system to detect when the encoder is falling behind and adjust cache write behavior accordingly, preventing cache thrashing while maintaining high-speed access when conditions permit.
2Productivity
If the display engine processes pixels quickly, then productivity is improved, but latency increases due to synchronization issues
Solution Approach 1:
The patent introduces a shared cache as an intermediary buffer between the display engine and encoder. This intermediary allows the display engine to write processed pixels at high speed without directly blocking the encoder. The cache absorbs the speed difference between pixel processing and encoding operations, enabling high productivity while preventing latency accumulation that would occur with direct synchronous processing.
3Speed
If the cache is used for storing pixel data, then access speed is improved, but frame drops occur due to cache eviction
Solution Approach 1:
The patent changes the parameter of cache write destination from a fixed setting to a dynamically selectable option. Instead of always writing to cache or always to memory, the system changes the destination parameter based on encoder synchronization status. This parameter change prevents cache eviction of critical encoder data by redirecting writes to memory when the encoder is behind, thereby maintaining frame continuity while preserving high-speed access benefits when conditions allow.
Data Source
AI summary
Particular embodiments described herein provide for an electronic device that can be configured to identify a frame in a video stream, process a pixel row in the frame using a display engine to create blended and/or composited pixels, determine a coding unit (CU) row in the frame an encoder is encoding, determine if a distance between the pixel row in the frame and the CU row in the frame satisfies a threshold, and store the blended and/or composited pixels from the display engine in a cache if the threshold is satisfied or store the blended and/or composited pixels in memory if the threshold is not satisfied.