Dynamic Virtual Address Remapping via Remap Vector
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory multi-mapping systems in GPUs are inefficient due to time-consuming page table updates and TLB cache invalidations, which complicate processor processing and software debugging.
Innovation Solution
A dynamic memory remapping technique using a remap vector to activate or deactivate virtual address groups without necessitating page table updates or TLB entry invalidations, allowing for efficient reconfiguration of virtual-to-physical address mappings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional page table updates and TLB cache invalidations are performed during virtual address remapping, then address mapping accuracy is maintained, but processing efficiency deteriorates due to time-consuming operations
Solution Approach 1:
The virtual address space is divided into multiple virtual address groups, each associated with a specific bit in the remap vector. This segmentation allows individual groups to be activated or deactivated independently without affecting other groups, enabling selective remapping that maintains accuracy while reducing the scope of required updates and invalidations.
Solution Approach 2:
The remap vector is pre-configured with the correct bit patterns representing the desired virtual address group mappings before actual address translation operations begin. This preliminary setup allows the system to switch between different virtual address group configurations instantly by simply updating the remap vector, avoiding time-consuming page table updates and TLB invalidations during runtime.
2Stability of the object's composition
If conventional page table updates are performed during virtual address remapping, then mapping consistency is maintained, but time consumption increases
Solution Approach 1:
Instead of modifying the actual page table structures during remapping operations, the patent uses a remap vector that serves as a simplified copy or representation of the virtual address group mapping state. Updates to the remap vector are much faster and do not require the complex page table update procedures, thereby maintaining mapping consistency while significantly reducing remapping time.
3Reliability
If TLB cache entry invalidations are performed during virtual address remapping, then cache coherence is maintained, but processing speed decreases
Solution Approach 1:
The remap vector is designed to be dynamically updateable without triggering TLB invalidations. The system dynamically switches between different virtual address group configurations by updating the remap vector bits, and the address translation mechanism is enhanced to check the remap vector status, allowing fast dynamic remapping while maintaining cache coherence through the remap vector's authoritative status.
4Manufacturing precision
If detailed page table updates are performed during remapping, then mapping precision is maintained, but system complexity increases
Solution Approach 1:
The patent extracts the essential remapping control function from the complex page table update mechanism and encapsulates it in the simplified remap vector structure. This extraction separates the high-level remapping control (handled by the simple remap vector) from the low-level address translation details (handled by existing page table and TLB mechanisms), thereby maintaining mapping precision while reducing overall system complexity.
Data Source
AI summary
For one or more stages of execution of a software application at a first processor, a remap vector of a second processor is reconfigured to represent a dynamic mapping of virtual address groups to physical address groups for that stage. Each bit position of the remap vector is configured to store a value indicating whether a corresponding virtual address group is actively mapped to a corresponding physical address group. Address translation operations issued during a stage of execution of the software application are selectively processed based on the configuration of the remap vector for that stage, with the particular value at the bit position of the remap vector associated with the corresponding virtual address group controlling whether processing of the address translation operation is continued to obtain a virtual-to-physical address translation sought by the address translation operation or processing of the address translation operation is ceased and a fault is issued.