Dynamic Virtual CPU Core Allocation for Cache Contention

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Solution Overview

Problem

Current power management algorithms in virtualized mobile platforms are inefficient due to their reliance on simple CPU utilization statistics, leading to performance degradation from cache contention and pollution, as they fail to consider cache utilization and other critical metrics.

Innovation Solution

Implementing cache and resource-aware power management that factors in cache utilization and other parameters to make informed decisions about CPU core remapping, ensuring efficient allocation of resources and minimizing cache collisions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple virtual machines share physical CPU cores and cache memory, then resource utilization improves, but cache contention and pollution increase leading to performance degradation

Engineering Contradiction:
Improveresource utilizationVSAvoidperformance stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements dynamic vCPU to physical core remapping based on runtime cache utilization metrics. The system continuously monitors cache performance and adjusts the mapping between virtual and physical CPU cores to minimize cache pollution and contention, transforming the static resource allocation into a dynamic adaptive system that responds to changing workload conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the mapping parameters between virtual CPUs and physical cores based on cache utilization metrics. By monitoring cache hit rates and pollution levels, the system remaps vCPUs to different physical cores to optimize cache performance, effectively changing the allocation parameters in response to measured system state.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If power management algorithms use simple CPU utilization statistics, then implementation complexity is reduced, but cache pollution and performance degradation occur

Engineering Contradiction:
Improvealgorithm complexityVSAvoidperformance stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces feedback mechanisms that monitor cache utilization metrics and use this information to guide vCPU remapping decisions. The system measures cache performance, feeds this information back to the power management algorithm, and adjusts resource allocation accordingly, creating a closed-loop control system that prevents cache pollution while maintaining manageable complexity.

Inventive Principle:
Principle #23Feedback

3Use of energy by moving object

If physical CPU cores are consolidated to reduce power consumption, then energy efficiency improves, but cache contention increases

Engineering Contradiction:
Improvepower consumptionVSAvoidcache contention
Core Design Contradiction:
Use of energy by moving objectVSObject-affected harmful factors

Solution Approach 1:

The system dynamically remaps virtual CPUs to physical cores based on real-time cache utilization monitoring. When consolidation is performed, the system continuously adjusts the mapping to distribute workloads in a way that minimizes cache pollution and contention, allowing aggressive consolidation while preventing the harmful effects through adaptive reallocation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent introduces an intermediary layer (the remapping mechanism) between the virtual machines and physical hardware. This intermediary monitors cache performance and mediates the allocation of physical cores to virtual machines, preventing direct cache contention even when multiple VMs share consolidated physical resources.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10372498B2Dynamic virtual CPU core allocation
Publication Date: 2019.08.06 INTEL CORP
  • US10372498B2 patent drawing
  • US10372498B2 patent drawing
  • US10372498B2 patent drawing

AI summary

The systems and methods described herein provide power management circuitry that factors one or more cache parameters (e.g., cache utilization) of an application or VM when determining pCPU-vCPU core remapping. By considering a more robust mix of both processor and cache memory related parameters, system performance and stability are increased by improving CPU and cache utilization and efficiency while reducing cache related issues such as collisions and/or pollution.