Dynamic VLIW Compiler for SIMD Branch Divergence
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Solution Overview
Problem
In computing systems with SIMD micro-architecture, the efficiency of parallel execution is reduced due to data-dependent work items where some execution units halt while others continue, leading to idle units and decreased throughput.
Innovation Solution
A compiler arranges instructions into dynamic variable-length instruction words (VLIWs) that intermingle instructions from different basic blocks between divergence and convergence points, allowing runtime assignment to parallel execution lanes based on branch directions, and updates the VLIW size and mapping to optimize execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional fixed-length instruction words are used in SIMD architecture, then hardware simplicity is maintained, but parallel execution efficiency deteriorates due to idle execution units at divergent branches
Solution Approach 1:
The patent applies dynamics by transitioning from fixed-length instruction words to variable-length VLIWs that adapt their size based on the number of active execution units at runtime. The instruction word length dynamically changes to match the actual workload, allowing efficient utilization of execution units whether they are all active or only a subset is needed due to branch divergence.
Solution Approach 2:
The patent segments the instruction stream into variable-length VLIWs that can be independently selected and executed. Each VLIW contains a specific number of instructions corresponding to the number of active execution units, allowing fine-grained control over which instructions are executed and when, thereby eliminating idle time in divergent branches.
2Loss of energy
If all execution units continue executing at divergent branches, then hardware utilization is maximized, but wasted work increases for units that should have taken different branches
Solution Approach 1:
The patent extracts and removes inactive execution units from the execution pipeline at divergent branches by using variable-length VLIWs that only include instructions for active units. This extraction prevents wasted energy consumption on units that should have taken different branches, while maintaining high throughput by ensuring only necessary instructions are executed.
3Productivity
If dynamic variable-length VLIWs are implemented, then execution unit utilization is optimized, but compiler complexity increases due to runtime assignment requirements
Solution Approach 1:
The patent applies preliminary action by having the compiler pre-arrange instructions into variable-length VLIWs and pre-compute the mapping between VLIWs and execution units based on branch directions. This preliminary preparation reduces runtime complexity and allows the system to achieve high execution unit utilization without excessive compiler or runtime overhead.
Data Source
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AI summary
A system and method for efficiently processing instructions in hardware parallel execution lanes within a processor. In response to a given divergent point within an identified loop, a compiler arranges instructions within the identified loop into very large instruction words (VLIW's). At least one VLIW includes instructions intermingled from different basic blocks between the given divergence point and a corresponding convergence point. The compiler generates code wherein when executed assigns at runtime instructions within a given VLIW to multiple parallel execution lanes within a target processor. The target processor includes a single instruction multiple data (SIMD) micro-architecture. The assignment for a given lane is based on branch direction found at runtime for the given lane at the given divergent point. The target processor includes a vector register for storing indications indicating which given instruction within a fetched VLIW for an associated lane to execute.