Dynamic Volatile Memory Cache Sizing Based on Flash Usage

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Solution Overview

Problem

Conventional systems require preallocation of DRAM memory for maximum flash-based cache configuration, leading to inefficient memory utilization and cumbersome upgrades, as they lack automated dynamic resizing of DRAM cache based on flash-based cache usage.

Innovation Solution

Implementing automated DRAM cache resizing logic that adjusts the size of the volatile memory cache based on user-selected flash-based cache configurations and sizing factors, using a formula and rules to reconfigure the DRAM cache, allowing for dynamic resizing and preserving user preferences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If DRAM memory is preallocated for maximum flash-based cache configuration, then flash-based cache capacity is ensured, but memory utilization efficiency deteriorates

Engineering Contradiction:
Improveflash-based cache capacityVSAvoidmemory utilization efficiency
Core Design Contradiction:
Quantity of substanceVSLoss of energy

Solution Approach 1:

The patent implements dynamic resizing of the DRAM cache based on the actual size of the flash-based cache configuration. Instead of fixed preallocation, the system automatically adjusts the DRAM cache size according to user selections and sizing factors, allowing the memory resource to adapt its capacity dynamically rather than remaining static at maximum potential size.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the allocation parameter of DRAM memory from a fixed maximum value to a variable value determined by flash-based cache usage. The system uses configuration and sizing factors as input parameters to calculate and adjust the appropriate DRAM cache size, transforming the memory allocation from a static quantity to a dynamically adjusted parameter.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If fixed preallocation of DRAM memory is used, then system configuration is simplified, but upgrade difficulty increases

Engineering Contradiction:
Improvesystem configuration simplicityVSAvoidupgrade difficulty
Core Design Contradiction:
Ease of manufactureVSEase of repair

Solution Approach 1:

The patent implements self-service through automated resizing logic that automatically adjusts the DRAM cache size based on user selections for flash-based cache configurations. The system performs the resizing operation autonomously without requiring manual intervention, thereby simplifying upgrades and reducing the burden on administrators while maintaining configuration simplicity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent performs preliminary action by automatically calculating and applying the correct DRAM cache size before the flash-based cache is fully configured or upgraded. The automated resizing logic proactively adjusts memory allocation in advance, eliminating the need for manual reconfiguration during upgrades and reducing human error.

Inventive Principle:
Principle #10Preliminary action

3Loss of energy

If automated DRAM cache resizing is implemented, then memory utilization improves, but device complexity increases

Engineering Contradiction:
Improvememory utilization efficiencyVSAvoidcache management complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms where the automated resizing logic continuously monitors flash-based cache configuration selections and sizing factors, then uses this feedback information to adjust the DRAM cache size accordingly. This closed-loop feedback system enables the cache management to automatically respond to changing conditions and optimize memory utilization dynamically.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces an intermediary component in the form of automated resizing logic that mediates between the flash-based cache configuration and the DRAM memory allocation. This intermediary layer handles the complexity of calculating and applying the correct memory size, shielding the rest of the system from direct complexity while enabling efficient memory utilization.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9043533B1Sizing volatile memory cache based on flash-based cache usage
Publication Date: 2015.05.26 EMC IP HLDG CO LLC
  • US9043533B1 patent drawing
  • US9043533B1 patent drawing
  • US9043533B1 patent drawing

AI summary

A method is used in sizing volatile memory (VM) cache based on flash-based cache usage. A user selection for a flash-based cache is received. Based on the selection, configuration and sizing factors are provided, by a flash based cache driver, to VM cache size determination logic. Based on the configuration and sizing factors and a sizing formula and rules, a requested VM cache size is produced by the VM cache size determination logic. Based on the requested VM cache size, the VM cache is caused, via VM cache resizing logic, to be resized to the requested VM cache size.