Dynamic Voltage Frequency Management for Multi-Processor Power Overload
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the number of transistors on semiconductor substrates increases and clock frequencies rise, power consumption in integrated circuits grows, leading to potential power supply overload in devices, especially in mobile devices, where excessive current draw can cause malfunctions due to supply voltage droop.
Innovation Solution
A system with multiple processors and an automatic power state controller (APSC) that dynamically adjusts operating points by limiting the number of active processors and using a digital power estimator (DPE) to throttle processors during high power consumption, ensuring the power supply capacity is not exceeded.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of transistors and clock frequencies are increased to improve processing capability, then productivity is improved, but power consumption increases causing power supply overload
Solution Approach 1:
The system dynamically adjusts the operating frequency of processors based on real-time power consumption monitoring. When power consumption approaches the power supply capacity limit, the system automatically reduces the operating frequency to maintain safe operation, enabling the system to adapt to power constraints while maximizing productivity when power is available
Solution Approach 2:
The system changes the operating parameters (frequency and voltage) of processors based on power consumption conditions. By programmatically adjusting these parameters in response to power supply capacity constraints, the system resolves the contradiction between maintaining high productivity and avoiding power overload
2Productivity
If all processors operate at high power points to maximize performance, then productivity is improved, but reliability deteriorates due to power supply voltage droop
Solution Approach 1:
The system implements a feedback mechanism where power consumption is continuously monitored and used to adjust processor operating points. When power consumption approaches the power supply capacity, the system reduces operating frequency to prevent voltage droop, ensuring reliable operation while maintaining optimal performance when power conditions permit
3Productivity
If operating frequency is increased to improve processing speed, then productivity is improved, but power consumption increases reducing device usage time
Solution Approach 1:
The system dynamically adjusts operating frequency based on power consumption monitoring to optimize the trade-off between processing speed and battery life. By reducing frequency when power consumption is high and maintaining higher frequency when power is available, the system extends device usage time while preserving productivity when needed
Data Source
AI summary
In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.