Dynamic Voltage Frequency Scaling Using Canonical Clock Models
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Solution Overview
Problem
Existing methods for dynamic voltage frequency scaling in integrated circuits are inefficient, either affecting yield by selecting optimal voltage and frequency during manufacturing or being costly in terms of resource usage and turn-around time by determining voltage and frequency pairings during design for multiple timing corners.
Innovation Solution
The method involves performing statistical timing analysis using a canonical form of a clock, expressing timing slack as a function of variability, and dynamically adjusting voltage and frequency based on a canonical model that considers sources of variability such as voltage, process, and random variations, thereby avoiding inefficient multi-corner computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage and frequency are selected during manufacturing to ensure optimal performance, then chip yield is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent implements dynamic voltage and frequency adjustment during chip operation rather than fixed selection during manufacturing. The system dynamically adapts voltage and frequency based on real-time performance requirements and power constraints, eliminating the need for complex manufacturing-time optimization while maintaining operational flexibility and yield.
Solution Approach 2:
The patent changes the parameters of voltage and frequency dynamically during operation based on statistical timing analysis and variability models. By using canonical forms to model timing slack as a function of variability sources, the system adjusts voltage and frequency parameters adaptively without requiring complex manufacturing processes.
2Manufacturing precision
If voltage and frequency pairings are determined during design for multiple timing corners, then design accuracy is improved, but resource usage and turn-around time increase
Solution Approach 1:
The patent performs statistical timing analysis and creates variability models during the design phase, but the actual voltage and frequency optimization is deferred to operation time. The preliminary work establishes the canonical forms and timing slack models, which then enable rapid adaptive adjustment during operation without requiring exhaustive multi-corner analysis at runtime.
Solution Approach 2:
The patent uses canonical forms as simplified mathematical representations that capture the essential variability behavior without requiring full multi-corner analysis. These canonical forms serve as models that can be quickly evaluated during operation to determine optimal voltage and frequency, replacing the computationally intensive exhaustive analysis.
3Speed
If higher chip frequency is implemented to improve performance, then speed is improved, but power consumption increases
Solution Approach 1:
The patent dynamically adjusts voltage and frequency based on real-time performance requirements and power constraints. When high performance is needed, the system increases both voltage and frequency; when power conservation is prioritized, it reduces both parameters, enabling flexible trade-off between speed and energy consumption during operation.
Solution Approach 2:
The patent changes voltage and frequency parameters adaptively based on statistical timing analysis results. By modeling timing slack as a function of variability sources including voltage, the system can optimize the voltage-frequency pairing to achieve desired performance with minimal power consumption, rather than using fixed high-performance settings.
Data Source
AI summary
A method, system, and computer program product to perform dynamic voltage frequency scaling of an integrated circuit include performing statistical timing analysis using a canonical form of a clock, the canonical form of the clock being a function of variability in voltage. Obtaining a canonical model expressing timing slack at each test location of the integrated circuit is as a function of one or more sources of variability, one of the one or more sources of variability being voltage, and performing the dynamic voltage-frequency scaling based on selecting at least one of a clock period and the voltage using the canonical model.