Dynamic Voltage Increment for Semiconductor Memory Erase
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Solution Overview
Problem
Current semiconductor devices employing incremental step pulse erase (ISPE) methods for memory cell operations face inefficiencies due to constant voltage increments in erase and program operations, which can lead to suboptimal threshold voltage distribution and increased operation times.
Innovation Solution
The semiconductor device and method involve dynamically increasing the voltage difference between successive erase and program loops, using variables to adjust the voltage increments based on verification outcomes, allowing for adaptive voltage adjustments to achieve target threshold levels more efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If constant voltage increment is used in incremental step pulse erase method, then erase operation can be performed systematically, but the number of loops required increases and operation time is extended
Solution Approach 1:
The patent applies dynamics by transitioning from a static constant voltage increment approach to a dynamic variable voltage increment approach. The voltage increment is adjusted based on the current erase state and verification results, allowing the system to adapt its step size during operation. This enables larger increments when appropriate and smaller increments when precision is needed, thereby reducing total operation time while maintaining threshold voltage distribution quality.
Solution Approach 2:
The patent implements parameter changes by modifying the voltage increment parameter during the erase operation. Instead of using a fixed Vstep value throughout all erase loops, the method dynamically adjusts the voltage increment based on verification outcomes and erase progress. This parameter adaptation allows optimization of both speed and precision, resolving the contradiction between operation time and threshold voltage control.
2Measurement precision
If multiple erase loops with verification are performed, then threshold voltage control precision is improved, but operation complexity and time increase
Solution Approach 1:
The patent employs feedback mechanisms where erase verification results are used to determine subsequent voltage increment values. The verification process provides feedback about the current threshold voltage state, and this information feeds back into the control logic that adjusts the voltage increment for the next erase loop. This closed-loop control achieves precise threshold voltage control while managing complexity through systematic decision-making based on verification outcomes.
Solution Approach 2:
The patent applies segmentation by dividing the erase operation into distinct loops with verification stages. Each erase loop is segmented into voltage application and verification phases, allowing systematic control and assessment. This segmentation enables precise control by breaking down the complex erase process into manageable, verifiable steps while maintaining overall operation efficiency.
3Productivity
If voltage increment is increased to reduce loops, then operation time decreases, but threshold voltage distribution precision deteriorates
Solution Approach 1:
The patent resolves this contradiction through dynamic adjustment of voltage increments. The system starts with appropriate increment sizes and adapts them based on verification results and erase progress. When verification indicates good progress, larger increments can be used to speed up operation; when precision is needed, smaller increments are applied. This dynamic approach maintains both speed and precision throughout the erase operation.
Solution Approach 2:
The patent applies local quality by using different voltage increment values at different stages of the erase operation and for different memory blocks. Instead of a uniform increment strategy, the method tailors the voltage increment to the specific needs of each erase loop based on verification outcomes. This localized optimization ensures precision where needed while maintaining overall productivity.
Data Source
AI summary
An operating method of a semiconductor device includes repeating an erase loop operable to lower threshold voltages of memory cells in a selected memory block by applying an erase voltage to the selected memory block and performing an erase verification to determine whether the threshold voltages of the memory cells in the selected memory block are less than or equal to a target level, wherein an erase voltage is increased by a voltage difference wherein the voltage difference is increased between successive applications of two or more of the erase loops, and repeating a program loop including applying a program voltage to a selected word line to increase threshold voltages of memory cells electrically coupled to the selected word line and performing a program verification to determine whether the threshold voltages are greater than or equal to a target level, wherein a program voltage is increased by a voltage difference wherein the voltage difference is increased between successive applications of two or more program voltages.