Dynamic Wear Leveling Threshold for Semiconductor Memory Blocks

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Solution Overview

Problem

Semiconductor devices experience wear degradation due to repeated erase and program operations, leading to reduced reliability in memory blocks with higher cycling numbers, necessitating effective wear management.

Innovation Solution

A semiconductor device with memory blocks, a circuit group for wear leveling, and a control circuit that sets threshold values based on cycling information to perform wear leveling operations, balancing wear across memory blocks by exchanging data between blocks with significant cycling number differences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wear leveling operations are performed frequently to balance wear across memory blocks, then reliability is improved, but productivity deteriorates due to increased operation overhead

Engineering Contradiction:
Improvememory block reliabilityVSAvoidoperation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent dynamically changes the wear leveling threshold parameter based on the average cycling number of memory blocks. When the average cycling number is high, a first threshold is used; when it is low, a second threshold is used. This parameter adaptation allows the system to adjust wear leveling frequency according to actual wear conditions, improving reliability when needed while maintaining productivity when wear is balanced.

Inventive Principle:
Principle #35Parameter changes

2Duration of action of stationary object

If wear leveling operations are performed to extend device lifespan, then duration of action is improved, but loss of time increases due to operation overhead

Engineering Contradiction:
Improvedevice lifespanVSAvoidwear leveling operation time
Core Design Contradiction:
Duration of action of stationary objectVSLoss of time

Solution Approach 1:

The patent implements partial wear leveling actions by comparing the difference between maximum and minimum cycling numbers against a dynamic threshold. Wear leveling is performed only when the difference exceeds the threshold, rather than continuously or uniformly across all memory blocks. This selective approach extends device lifespan by addressing wear imbalance only when necessary, while minimizing time loss by avoiding unnecessary operations.

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If threshold value is set low to detect wear imbalance early, then measurement precision is improved, but productivity deteriorates due to more frequent wear leveling operations

Engineering Contradiction:
Improvewear imbalance detection precisionVSAvoidoperation efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent makes the threshold value dynamic rather than fixed. The threshold is adjusted based on the average cycling number of memory blocks, changing from a first threshold when average cycling is high to a second threshold when average cycling is low. This dynamic adjustment maintains high measurement precision for wear imbalance detection while adapting productivity requirements based on the actual wear state of the memory blocks.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9564246B2Semiconductor device and operating method thereof
Publication Date: 2017.02.07 MIMIRIP LLC
  • US9564246B2 patent drawing
  • US9564246B2 patent drawing
  • US9564246B2 patent drawing

AI summary

A semiconductor device includes: memory blocks including main data storage units and cycling information storage units; a circuit group that performs a wear leveling operation on the memory blocks; and a control circuit that sets a threshold value based on the cycling information, and controls the circuit group so that the wear leveling operation is performed based on the set threshold value.