Dynamic Word Line Drivers for Memory Arrays
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Solution Overview
Problem
Traditional dynamic/static memory systems place a heavy load on the clock, leading to increased complexity, power consumption, and capacitive noise coupling between wordline driver outputs, necessitating improved wordline drivers.
Innovation Solution
The implementation of a circuit device with selectively activated wordline drivers, where a clock signal is provided to a selected group of drivers based on a memory address, reducing capacitive coupling and power consumption by using multiple conditional clocks and sharing a common address signal among multiple decoders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single clock drives multiple wordline drivers and decoders, then the system operates with unified timing control, but the electrical load on the clock increases significantly
Solution Approach 1:
The patent divides the clock distribution system into multiple segments by providing separate clock signals to different groups of wordline drivers. Instead of one clock driving all drivers, the system uses multiple clocks (e.g., clock0, clock1, clock2, clock3) each driving a specific group of drivers, thereby segmenting the load and reducing the electrical burden on any single clock source while maintaining synchronized control.
Solution Approach 2:
The patent implements partial clock distribution where not all wordline drivers receive the clock signal simultaneously. Only the drivers corresponding to the currently active memory bank or tile receive their clock signals, while others remain inactive. This partial action approach reduces the overall electrical load on the clock system compared to driving all drivers continuously.
2Ease of operation
If each wordline driver has its own decoded address input, then address decoding is distributed, but the decoder load and circuit substrate area increase
Solution Approach 1:
The patent merges the address decoding function into a centralized decoder unit that serves multiple wordline driver groups. Instead of each driver having its own decoder, a single decoder (or limited number of decoders) generates control signals that are distributed to multiple drivers. This combining approach reduces the total decoder load and minimizes the circuit substrate area required for decoding logic.
Solution Approach 2:
The patent introduces intermediary control logic that sits between the address input and the wordline drivers. This intermediary layer processes the address signals and generates appropriate control signals for multiple drivers, acting as a mediator that reduces the direct decoding burden on individual drivers while maintaining distributed control capabilities.
3Device complexity
If a single clock drives multiple wordline drivers, then timing is simplified, but capacitive noise coupling between driver outputs increases
Solution Approach 1:
The patent segments the clock distribution to different driver groups using separate clock signals. By providing different clock signals (e.g., clock0, clock1, clock2, clock3) to different groups of wordline drivers, the system reduces simultaneous switching activity across all drivers. This segmentation of clocking reduces capacitive noise coupling between driver outputs while maintaining manageable timing control through phased clock distribution.
Data Source
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AI summary
In a particular illustrative embodiment, a circuit device that includes first logic and second logic is disclosed. The first logic receives a clock signal and a first portion of a memory address of a memory array, decodes the first portion of the memory address, and selectively applies the clock signal to a selected group of wordline drivers associated with the memory array. The second logic decodes a second portion of the memory address and selectively activates a particular wordline driver of the selected group of wordline drivers according to the second portion of the memory address.