Dynamic Wordline Biasing for Fast and Stable Memory Cell Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In phase-change memory cells, achieving precise and rapid current application is challenging due to the limitations of single source followers, which result in slow charging times and susceptibility to process variations, and the risk of memory cell state changes during reading operations.
Innovation Solution
The gate bias voltage of the source follower is boosted initially to increase charging speed, and then lowered after a predetermined time to prevent state changes during reading, with a current mirror used to bleed off charge and reduce the time needed to reach the desired voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single source follower is used to provide current to the memory cell, then the circuit area is small, but the charging time is slow and the operation is susceptible to process variations
Solution Approach 1:
The patent divides the single source follower into multiple source followers (first source follower and second source follower) that operate in sequence. The first source follower charges the bit line initially, then the second source follower takes over to complete the charging. This segmentation allows faster charging while keeping each individual source follower compact, thus maintaining small circuit area while improving charging speed.
Solution Approach 2:
The patent implements dynamic switching between different source followers based on the charging state. A control circuit dynamically selects which source follower is active at any given time, allowing the system to adapt the charging current dynamically. This dynamic operation enables faster charging times while maintaining circuit compactness through selective activation of components.
2Speed
If the source follower provides continuous current to charge the bit line quickly, then the charging speed is fast, but the memory cell state may change during the read operation
Solution Approach 1:
The patent applies a higher initial gate bias voltage to the first source follower to rapidly charge the bit line to the required voltage level before the read operation begins. This preliminary fast charging action completes the bit line charging in advance, allowing the subsequent read operation to proceed with stable, lower current that prevents memory cell state changes.
Solution Approach 2:
The patent uses periodic switching between different source followers with different bias conditions. The first source follower operates with higher current for an initial period to charge the bit line rapidly, then switches to the second source follower with lower current for the remainder of the operation. This periodic action sequence achieves both fast charging and memory cell state stability.
3Loss of time
If the gate bias voltage is kept high to maintain fast charging, then the charging time is reduced, but process variations have greater impact on the operation
Solution Approach 1:
The patent changes the gate bias voltage parameter dynamically during the operation. The first source follower receives a higher gate bias voltage initially to achieve fast charging, then the bias voltage is reduced or switched to a different configuration for the second source follower. This parameter change allows the system to achieve fast charging when needed while reducing sensitivity to process variations during the stable reading phase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster and more precise current application, reducing the impact of process variations and preventing memory cell state changes during read operations, thereby improving the reliability of memory cell state reading.
Implementation Method 1
a source follower to charge a bit line corresponding to the memory cell
Implementation Method 2
a current mirror used to bleed off charge and reduce the time needed to reach the desired voltage
Data Source
AI summary
Techniques for dynamically biasing memory cells are disclosed. In the illustrative embodiment, a source follower sets a voltage on a wordline of a memory cell. A bias voltage on the gate of the source follower can be temporarily increased in order to charge the wordline more quickly. In some embodiments, for a read operation, after a demarcation voltage has been applied to the memory cell for the memory cell to change its resistance if it is set, the bias voltage on the gate of the source follower is decreased in order to prevent the memory cell from changing its resistance while the current through the memory cell is being read. In some embodiments, a current mirror can be activated in order to bleed off charge from the wordline to lower the voltage more quickly.