Dynamic Wordline Delay for NAND Read Access Optimization
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Solution Overview
Problem
In memory devices, particularly non-volatile memory devices like NAND, the read access time is prolonged due to wordline resistive-capacitive (RC) variations and transistor threshold voltage differences, leading to hot carrier injection issues, as the pillar potential is difficult to control accurately, resulting in unnecessary delays during the Vpass period.
Innovation Solution
Implementing control logic to dynamically determine the delay time added to the Vpass period based on the state of the selected wordline, customizing the delay to the specific pillar or channel state, allowing for shorter delays when the pillar is in a transient state and longer delays when it's in a stable state, thereby optimizing read access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed delay time is added to the Vpass period to ensure accurate pillar potential control, then hot carrier injection risks are reduced, but read access time is prolonged
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed delay time to a dynamic, state-dependent delay time. The control logic monitors the pillar state (stable or transient) and adjusts the delay time accordingly - using a longer delay when the pillar is in a stable state to prevent hot carrier injection, and a shorter delay when the pillar is in a transient state where hot carrier injection risk is naturally reduced. This dynamic adjustment resolves the contradiction by making the delay adaptive rather than static.
Solution Approach 2:
The patent changes the parameter of delay time based on the pillar state. Instead of using a single fixed delay value, the system varies the delay parameter according to whether the pillar is in a stable or transient state. This parameter change allows optimization of read access time while maintaining reliability - the delay is extended only when necessary (stable state) and reduced when safe (transient state).
2Device complexity
If wordline RC variations and transistor threshold voltage differences are not compensated, then device complexity is reduced, but read access time increases due to unnecessary delays
Solution Approach 1:
The patent implements feedback by having the control logic monitor the pillar state (which reflects the actual voltage conditions affected by wordline RC variations and transistor threshold differences) and use this information to adjust the delay time. This feedback mechanism allows the system to compensate for process variations dynamically without requiring complex pre-characterization or compensation circuits, thus resolving the contradiction between simplicity and performance.
Solution Approach 2:
The system performs self-service by using the natural transient state information already present in the pillar to guide its own operation. When the pillar is in a transient state, the system automatically recognizes this condition and reduces the delay time without external intervention or complex control algorithms. This self-service approach maintains simplicity while improving read access time.
Data Source
AI summary
A memory device includes an array of memory cells associated with multiple wordlines and control logic operatively coupled with the array. The control logic, in performing a read operation, can determine a length of time that a selected wordline, of the multiple wordlines, takes to reach a pass voltage for reading data from a memory cell associated with the selected wordline. The control logic can select a delay time based on whether the length of time is associated with a transient state or a non-transient state. The control logic can read the data from the memory cell associated with the selected wordline after the selected delay time.