Dynamic Write Policy for Multi-Core Cache Coherence
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Solution Overview
Problem
Current cache coherence protocols in multi-core systems are complex, costly, and inefficient, requiring directories, invalidations, broadcasts, and snoops, which increase hardware costs and power consumption while compromising performance.
Innovation Solution
A dynamic write policy is implemented that classifies cache lines as private or shared, allowing for write-back or write-through operations, eliminating the need for directories, invalidations, and snoops, and simplifying the cache coherence protocol to two stable states (Valid/Invalid) with optional transient dirty states for shared cache lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If directory-based cache coherence protocols are used to maintain coherence in multi-core systems, then coherence reliability is improved, but device complexity and storage requirements increase significantly
Solution Approach 1:
The patent extracts and removes the directory structure from the cache coherence system entirely. Instead of using a directory to track shared data and manage invalidations, the system relies on individual cache line state bits (valid, dirty, shared) and a simplified protocol that eliminates the need for directory-based tracking, reducing structural complexity while maintaining coherence
Solution Approach 2:
The patent changes the state parameters of cache lines from the traditional multi-state directory protocol (requiring 30+ states) to a simplified model with only three stable states (valid, invalid, dirty) and optional transient dirty states. This parameter reduction dramatically simplifies the protocol logic and storage requirements while preserving coherence guarantees
2Reliability
If directory-based cache coherence protocols with constant tracking and invalidations are implemented, then coherence reliability is improved, but use of energy increases due to frequent broadcasts and snoops
Solution Approach 1:
The patent implements self-service coherence where each core independently determines whether data is shared or private through classification mechanisms, and manages its own cache line states without requiring centralized directory coordination. This eliminates frequent invalidation broadcasts and snoop operations, significantly reducing energy consumption while maintaining coherence through autonomous cache management
Solution Approach 2:
The patent introduces periodic or event-driven coherence validation at synchronization points rather than continuous tracking. Cache lines are validated and states are updated at structured intervals or upon specific events (synchronization barriers, memory fences), reducing the frequency of coherence operations and associated energy consumption compared to continuous directory-based invalidation
3Reliability
If complex cache coherence protocols with multiple states are used, then coherence reliability is improved, but manufacturing cost increases due to additional storage and logic requirements
Solution Approach 1:
The patent removes the directory structure and associated complex logic from the system, eliminating the need for additional storage resources and complex control logic that would increase manufacturing cost. The simplified protocol uses only essential cache line state bits already present in standard cache designs
Solution Approach 2:
The patent makes existing cache infrastructure multi-functional by using the same cache structure and state bits for both data storage and coherence management. The valid, dirty, and shared bits serve dual purposes of tracking data state and enabling coherence decisions, eliminating the need for separate directory structures and reducing manufacturing complexity
4Reliability
If traditional cache coherence protocols are implemented in many-core systems, then coherence reliability is improved, but device complexity becomes prohibitive for scaling to many cores
Solution Approach 1:
The patent segments the coherence management responsibility from a centralized directory to individual cache lines and individual cores. Each cache line independently tracks its own state (valid, dirty, shared), and each core independently manages its cached data, enabling the system to scale to many cores without proportionally increasing protocol complexity
Solution Approach 2:
The patent reduces the number of coherence states from 30+ in traditional directory protocols to just three stable states (valid, invalid, dirty) with optional transient dirty states. This dramatic parameter reduction makes the protocol manageable and verifiable even in many-core systems where protocol complexity would otherwise be prohibitive
Data Source
AI summary
System and methods for cache coherence in a multi-core processing environment having a local/shared cache hierarchy. The system includes multiple processor cores, a main memory, and a local cache memory associated with each core for storing cache lines accessible only by the associated core. Cache lines are classified as either private or shared. A shared cache memory is coupled to the local cache memories and main memory for storing cache lines. The cores follow a write-back to the local memory for private cache lines, and a write-through to the shared memory for shared cache lines. Shared cache lines in local cache memory enter a transient dirty state when written by the core. Shared cache lines transition from a transient dirty to a valid state with a self-initiated write-through to the shared memory. The write-through to shared memory can include only data that was modified in the transient dirty state.