Dynamic Write Pulse Width Control for STT-MRAM Error Reduction
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Solution Overview
Problem
MRAMs, particularly STT-MRAMs, face higher write error probabilities and slower access speeds due to the time-consuming verification process and increased power consumption associated with writing data, which hampers their performance as cache or main memory in portable information terminals.
Innovation Solution
A memory system with a non-volatile MRAM and a memory controller that manages write pulse width based on storage free space and access information, employing two modes: one with verification for high-speed writing and another with longer pulse width for reduced error probability, optimizing write operations by batch processing verification and adjusting pulse width according to command ratios and storage availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a verification process is performed to write data and then read and verify the data, then write reliability is improved, but access speed deteriorates
Solution Approach 1:
The patent applies partial verification by selectively performing read-verify operations based on write error probability assessments. Instead of verifying every write operation, the system performs verification only when necessary (when error probability is high), thus reducing the overall verification overhead while maintaining adequate reliability. This is achieved by monitoring write conditions and dynamically deciding whether to execute the verification read operation.
2Reliability
If a verification process is performed to write data and then read and verify the data, then write reliability is improved, but power consumption increases
Solution Approach 1:
The patent reduces power consumption by performing partial verification operations only when write error probability is high. The verification read operation is omitted when error probability is low, thereby reducing unnecessary power consumption. This selective approach balances reliability requirements with power efficiency, especially important for portable devices.
3Reliability
If a write pulse width is lengthened, then write error probability is reduced, but access speed deteriorates
Solution Approach 1:
The patent dynamically adjusts the write pulse width based on real-time assessment of write error probability. Instead of using a fixed long pulse width for all writes, the system selects between short and long pulse widths depending on the specific write conditions and estimated error probability. This dynamic adaptation allows the system to achieve reliable writes when necessary while maintaining high speed when possible.
Solution Approach 2:
The patent changes the write pulse width parameter based on assessed write error probability. When error probability is high, the system increases the pulse width to ensure reliable writing. When error probability is low, the system uses a shorter pulse width to maintain high access speed. This parameter adjustment is made dynamically based on write conditions.
4Reliability
If a write voltage is raised, then write error probability is reduced, but power consumption increases
Solution Approach 1:
The patent dynamically adjusts write voltage based on assessed write error probability. Instead of continuously operating at high voltage to ensure reliability, the system raises voltage only when necessary (when error probability is high) and operates at lower voltage when writes are likely to succeed. This dynamic voltage scaling reduces average power consumption while maintaining adequate reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances write speed and reduces error probabilities in MRAMs by strategically managing write pulse widths and verification processes, thereby improving access performance and power efficiency in processor systems.
Implementation Method 1
a perpendicular-magnetization spin transfer mode, referred to as an STT-MRAM (Spin Transfer Torque MRAM), is expected for a variety of applications
Data Source
AI summary
A memory system has a non-volatile memory, a storage accessible at higher speed than the non-volatile memory, to store access information to the non-volatile memory before accessing the non-volatile memory, and a memory controller to control a write pulse width to the non-volatile memory based on a free space of the storage or based on the access information stored in the storage.