Dynamic Write Time Control for Resistance Change Memory

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Resistance change memory technologies, such as MRAM, wastefully consume current during write operations due to a fixed write time that does not account for varying write times across memory cells, leading to unnecessary current flow through cells that require no writing or have already completed writing.

Innovation Solution

Incorporating a write buffer with a current/voltage converter that converts write current into sense voltage, allowing for dynamic adjustment of write time per memory cell column, and using a sense amplifier to detect when the sense voltage exceeds a threshold, thereby reducing unnecessary current flow by stopping the write operation earlier for completed cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a fixed write time is used for all memory cells, then the write operation is simple to control, but unnecessary current flows through memory cells that have completed writing or require no writing

Engineering Contradiction:
Improvewrite control complexityVSAvoidwrite current consumption
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The patent implements a feedback mechanism where the sense amplifier continuously monitors the voltage on the bit line during the write operation. When the voltage change indicates that the memory cell has completed writing (or requires no writing), the sense amplifier generates a feedback signal to the write buffer, which then terminates the write current. This feedback-based approach dynamically adjusts the write duration for each memory cell, eliminating unnecessary current consumption while maintaining simple overall control architecture.

Inventive Principle:
Principle #23Feedback

2Reliability

If the write time is extended to accommodate all memory cells, then all cells can be written, but current is wasted on cells that completed writing earlier

Engineering Contradiction:
Improvewrite completion reliabilityVSAvoidexcessive write time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent transitions from a static fixed write time approach to a dynamic write time approach. The write operation duration is dynamically adjusted for each memory cell based on real-time monitoring of the bit line voltage. The sense amplifier detects when each individual cell has completed writing, and the write buffer dynamically terminates the current accordingly. This dynamic adjustment ensures reliable write completion for all cells while minimizing the write time for each cell, eliminating the need to extend write time for the slowest cell.

Inventive Principle:
Principle #15Dynamics

3Reliability

If write current is continuously applied, then all memory cells are ensured to be written, but power consumption increases due to unnecessary current flow

Engineering Contradiction:
Improvewrite operation reliabilityVSAvoidpower consumption during write
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent employs a feedback mechanism where the sense amplifier monitors the bit line voltage during the write operation and provides feedback to the write buffer. When the voltage change indicates that a memory cell has completed writing (or requires no writing), the feedback signal causes the write buffer to terminate the write current for that cell. This ensures reliable write operation for cells that need writing while eliminating unnecessary current flow and power consumption for cells that have already been written or require no writing.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces power consumption by minimizing wasteful current flow during write operations, achieving lower power consumption comparable to SRAM caches while maintaining nonvolatility and high-speed memory characteristics.

Implementation Method 1

a resistance change element connected between first and second conductive lines

Methodology Applied
Scientific EffectMagnetoresistive effect: Magnetoresistance

Data Source

PatentUS8902636B2Resistance change memory
Publication Date: 2014.12.02 KIOXIA CORP
  • US8902636B2 patent drawing
  • US8902636B2 patent drawing
  • US8902636B2 patent drawing

AI summary

According to one embodiment, a memory includes a resistance change element connected between first and second conductive lines, a write buffer which writes data in the resistance change element by flowing a write current to the resistance change element through the first and second conductive lines in a writing, a current/voltage converter which converts the write current into a sense voltage, the converter provided in the write buffer, the write buffer being non-activated when the sense voltage is larger than a first threshold value.