Dynamic XOR Parity Mapping in Flash Memory
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Solution Overview
Problem
Existing flash memory devices face issues with error correction overhead due to static XOR parity placement, which can lead to increased dependency on error-prone memory dies and wasted space in memory systems.
Innovation Solution
Implementing a dynamic reconfiguration of parity memory cells, where the memory controller relocates or duplicates parity cells based on performance data to avoid error-prone areas, thereby reducing dependency on defective dies and optimizing parity distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static XOR parity placement is used in flash memory devices, then error correction can be performed, but computational overhead increases and dependency on error-prone memory dies increases
Solution Approach 1:
The patent implements dynamic reconfiguration of parity memory cells, where the memory controller monitors performance data and relocates or duplicates parity cells based on real-time memory die health status. This transforms the static parity placement into a dynamic system that adapts to changing memory conditions, reducing dependency on error-prone dies while maintaining error correction capability
Solution Approach 2:
The system continuously monitors performance data from memory dies and uses this feedback to make informed decisions about parity cell placement. The memory controller adjusts parity configuration based on observed error patterns and die reliability, creating a closed-loop system that optimizes error protection while minimizing computational overhead
2Reliability
If static XOR parity placement is used in flash memory devices, then error correction can be performed, but memory space is wasted
Solution Approach 1:
The patent changes the configuration parameters of parity memory cells dynamically based on memory die performance. By adjusting the number and location of parity cells according to observed error rates and die health, the system optimizes the balance between error protection and memory space utilization, avoiding waste of memory resources on overly conservative static allocation
3Reliability
If parity data is relocated away from error-prone components, then error protection is enhanced, but system complexity increases
Solution Approach 1:
The patent implements parity cell duplication as a strategy to protect against errors in relocated parity cells. By creating redundant copies of parity data in multiple locations, the system enhances error protection while managing reconfiguration complexity through standardized copy operations that can be automated by the memory controller
Data Source
AI summary
A storage device includes multiple memory dies and a controller configured to: (i) perform XOR parity computations for parity bins based, at least in part, on updated contents of a first user data memory cell and contents of each user data memory cell also assigned to the first parity bin, (ii) storing the first parity data into a first parity memory cell associated with the first parity bin; (iii) identify a second parity memory cell for dynamic reconfiguration based, at least in part, on performance data of the non-volatile memory device, the second parity memory cell being assigned to a second parity bin; (iv) copy the second parity memory cell to a third memory cell of the plurality of memory cells; and (v) associate the third memory cell with the second parity bin, thereby making the third memory cell a parity memory cell of the plurality of parity memory cells.