E-graph Rewriting for High-Level Synthesis Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-level synthesis tools produce hardware designs that are less efficient and performant compared to manually implemented designs, due to inefficiencies in translating software programs into hardware descriptions at the Register Transfer Level (RTL).
Innovation Solution
A super-optimization explorer using E-graph rewriting (SEER) is employed to generate optimized HLS code by exploring multiple representations of an input program, enabling the synthesis of RTL with improved performance and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If high-level synthesis tools are used to translate software programs into hardware descriptions, then automation extent is improved, but manufacturing precision deteriorates
Solution Approach 1:
The translation process is segmented into multiple phases: initial HLS translation, e-graph construction from the translated RTL, exploration of alternative representations through rewriting rules, and selection of optimized implementations. This segmentation allows automated tools to operate at each phase while progressively improving precision through structured exploration and verification.
Solution Approach 2:
The system performs preliminary actions by constructing e-graphs that capture multiple equivalent representations of the hardware logic before final synthesis. Rewriting rules are applied in advance to explore optimization opportunities, and verified implementations are selected before the final RTL generation, ensuring precision is improved before the automated translation completes.
2Manufacturing precision
If e-graph rewriting exploration is performed to generate optimized HLS code, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
E-graphs serve as an intermediary data structure between the input program and the final RTL output. The rewriting system operates on this intermediate representation, exploring multiple equivalent implementations without requiring direct manipulation of the original code or final hardware description. This intermediary layer manages complexity by providing a structured, canonical form for exploration.
Solution Approach 2:
The system creates multiple copies of the hardware logic representation within the e-graph, where each node may have multiple uses and equivalent transformations are explored through copying and rewriting. This allows the system to evaluate multiple implementations of the same logic without modifying the original design, managing complexity through systematic duplication and comparison.
3Productivity
If multiple representations of input program are explored, then productivity is improved, but loss of time increases
Solution Approach 1:
The system applies partial exploration by selectively applying rewriting rules based on heuristics and cost functions, rather than exhaustively exploring all possible representations. Verified implementations are selected when sufficient optimization is achieved, balancing the time invested in exploration against the quality improvement of the final HLS implementation.
Solution Approach 2:
The system uses feedback through cost functions and verification mechanisms to guide the exploration process. Rewriting rules that improve performance metrics are retained and applied further, while unproductive transformations are pruned. This feedback loop enables the system to focus exploration on promising paths, reducing time loss while maintaining productivity.
Data Source
AI summary
Described herein is a technique and associated tool for automatic program code optimization for high-level synthesis. The tool can efficiently explore multiple representations of an input program using e-graph rewriting and determine an HLS-efficient representation of program code for input into high-level synthesis tools.