E-graph Rewriting for RTL Circuit Equivalence Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Commercial RTL equivalence checking tools face challenges in determining which word-level rewrites to apply and in what order to verify circuit designs effectively, leading to unclear paths between architectures at the register transfer level (RTL) abstraction.
Innovation Solution
The proposed solution involves generating graph representations of circuit designs, joining them into an equivalence graph (e-graph), and applying rewrites to add logically equivalent operators, allowing for the extraction of shared designs and validation using an integer linear program solver, thereby simplifying the verification process and enhancing the capabilities of traditional equivalence checking tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional equivalence checking tools are used, then verification can be performed, but it is unclear which rewrites to apply and in what order to find a path between architectures
Solution Approach 1:
The e-graph system automatically manages the complexity of rewrite application by maintaining an equivalence graph that tracks all possible rewrite paths. The system self-navigates through the graph to find equivalence paths between architectures, eliminating the need for manual intervention in selecting and ordering rewrites.
Solution Approach 2:
The e-graph serves as an intermediary data structure between the input architectures and the verification result. It mediates the complex rewrite process by organizing all possible transformations in a graph structure, allowing the system to navigate from one architecture to another through intermediate equivalent forms.
2Reliability
If word-level rewrites are applied to verify equivalence, then verification capability is enhanced, but traditional tools cannot prove certain equivalence cases
Solution Approach 1:
The e-graph system provides universal verification capability by handling multiple types of architectures and rewrite patterns within a single unified framework. It can process diverse architectural styles and apply appropriate rewrites automatically, making it adaptable to various verification scenarios that traditional tools cannot handle.
Solution Approach 2:
The system dynamically adapts its verification strategy by automatically selecting which rewrites to apply based on the specific architecture being verified. The e-graph structure allows flexible navigation through different rewrite paths, enabling the system to adapt to diverse architectural patterns and prove equivalence cases that require non-standard rewrite sequences.
Data Source
AI summary
A device, method, and non-transitory computer-readable medium for generating one or more equivalent designs between a first and second circuit designs. Graphs for the first and second design are created each consisting of vertices representing operators and operands, with edges representing relationships between them. These graphs are combined into a third graph that is modified to include multiple logically equivalent designs to the original two designs by determining equivalent operators for certain vertices. From the logically equivalent designs in the third graph, a set of shared designs is extracted, consisting of vertices that are common between the equivalent designs in the first and second graphs. These shared designs may be expressed in a register transfer level (RTL) representation for validation and equivalence checking.