E2 Communication Forwarding with IP Mapping for Near-RT RIC Latency

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Solution Overview

Problem

The introduction of IPSec on the E2 interface in O-RAN communication systems impacts latency, potentially failing to meet the required latency of between 10 milliseconds and 1 second for Near-RT RIC operations.

Innovation Solution

Forwarding E2 communication based on a mapping between IP addresses of E2 Termination Instances and E2 Nodes, allowing direct transmission of data without IPSec overhead, thereby maintaining latency within the required range.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If IPSec is implemented on the E2 interface to protect communication, then security and reliability are improved, but latency increases and may fail to meet the 10 milliseconds to 1 second requirement

Engineering Contradiction:
Improvecommunication securityVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system segments the E2 interface communication into two paths: a control plane path that uses IPSec for security, and a user plane path that bypasses IPSec for low-latency data transmission. This segmentation allows security requirements to be met for control signaling while maintaining low latency for time-sensitive user data.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system introduces an intermediary forwarding mechanism that sits between the E2 interface and the Near-RT RIC, capable of intelligently routing packets through IPSec-protected paths or direct paths based on packet type and latency requirements. This intermediary enables selective application of security protocols without forcing all traffic through the slower secured path.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If direct transmission without IPSec is used, then latency is reduced and Near-RT RIC requirements are met, but security protection is lost

Engineering Contradiction:
ImprovelatencyVSAvoidcommunication security
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The system applies different quality characteristics to different parts of the communication: control plane traffic receives full IPSec security protection, while user plane traffic receives selective or no security processing. This local differentiation allows each traffic type to receive the appropriate level of security without unnecessary overhead.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system dynamically changes security parameters (such as encryption enabled/disabled, protocol selection) based on traffic type, latency requirements, and network conditions. This allows the security level to be adjusted per-packet or per-flow, optimizing the balance between security and latency.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If IPSec overhead is applied to all E2 communication, then comprehensive security is achieved, but processing complexity and latency increase

Engineering Contradiction:
Improvecomprehensive securityVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system applies security processing partially rather than excessively to all traffic. By identifying and exempting time-sensitive user plane traffic from full IPSec processing, the system achieves adequate security for control functions while avoiding the excessive complexity and latency that would result from universal IPSec application.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12445497B2Apparatus, method, and computer program for forwarding E2 communication in a network
Publication Date: 2025.10.14 RAKUTEN SYMPHONY INC
  • US12445497B2 patent drawing
  • US12445497B2 patent drawing
  • US12445497B2 patent drawing

AI summary

Provided are apparatus, method, and device capable of forwarding E2 communication a network. According to embodiments, the apparatus may include: at least one memory storage storing computer-executable instructions; and at least one processor communicatively coupled to the at least one memory storage, wherein the at least one processor may be configured to execute the instructions to: obtain a mapping between a first IP address of an instance of E2 Termination deployed at the Near-RT RIC and at least one second IP address of at least one E2 node associated with the instance of E2 Termination; receive a data from an E2 node; determine whether to directly transmit the data to the instance of E2 Termination based on the mapping.