EA Directory Marking for TLB Invalidation Draining
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Solution Overview
Problem
In multiprocessor computer systems, the invalidation of page table entries in translation lookaside buffers across multiple processor cores is serialized, leading to performance penalties and potential stalls or deadlocks due to the need for strict synchronization during memory-mapped I/O operations.
Innovation Solution
A method where a processor core calculates a target effective address, allocates an array entry in an upper-level cache, and buffers memory-referent requests with a pointer to the entry in an EA directory. Upon receiving a translation invalidation request, the core walks the EA directory to match the address range and marks in-flight requests, allowing the invalidation to complete only after the requests have drained from the processing unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TLB invalidate entry instructions are strictly serialized across processor cores, then coherency of address translations is maintained, but system productivity and performance are significantly degraded
Solution Approach 1:
The patent segments the TLB invalidation process into two independent parts: (1) broadcasting the invalidation request to all processor cores, and (2) draining in-flight memory-referent requests. This allows the invalidation broadcast to proceed without waiting for request completion, while request draining occurs independently, eliminating the serialization bottleneck while maintaining coherency.
Solution Approach 2:
The patent performs preliminary marking of in-flight memory-referent requests with invalidation information before the invalidation completes. By pre-identifying and marking requests that need to be drained, the system prepares the necessary state information in advance, allowing the invalidation to proceed without blocking productive operations.
2Reliability
If synchronization instructions are added to guarantee TLB entry invalidation completion, then coherency is ensured, but execution time and latency increase
Solution Approach 1:
The patent extracts the coherency guarantee mechanism from the critical execution path by using implicit marking of in-flight requests rather than explicit synchronization instructions. The marking is performed as a side effect of the invalidation process itself, removing the need for additional time-consuming sync operations while maintaining coherency.
Solution Approach 2:
The system uses self-service coherency tracking where the invalidation process automatically marks its own dependent requests during execution. Instead of requiring external synchronization mechanisms to track and guarantee coherency, the invalidation operation itself maintains the necessary state information through automatic marking, reducing time loss.
3Productivity
If multiple processor cores share common queues and buffers, then resource utilization is improved, but stalls and deadlocks occur during TLB invalidation
Solution Approach 1:
The patent introduces marking information as an intermediary mechanism that mediates between the shared queues/buffers and the TLB invalidation process. By attaching marking information to in-flight requests, the system can track which requests need to be drained without blocking the shared resources, allowing other cores to continue utilizing the queues and buffers while maintaining system stability.
Data Source
AI summary
A memory-referent instruction is executed to calculate a target effective address (EA) of a corresponding memory-referent request. An array entry in an upper level cache is allocated, and the EA is specified in a corresponding EA directory entry. While in-flight, the memory-referent request is buffered in a queue in association with a pointer to the entry in the EA directory. Based on receiving a translation invalidation request requesting invalidation of an address translation in a translation structure, the processor core walks the EA directory, determines the EA in the entry matches an address range specified by the translation invalidation request, and, based on the match, precisely marks the memory-referent request using the pointer to the EA directory entry. Based on the marking, the translation invalidation request is permitted to complete with reference to the processor core only after the memory-referent request has drained from the processing unit.