Effective Address Directory and Table for Out-of-Order Load Translation
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Solution Overview
Problem
Out-of-order (OoO) processors face challenges in managing hazards and efficient address translation due to the execution of younger load instructions before older store instructions, leading to pipeline flushes and performance penalties, and existing solutions are inefficient in tracking effective addresses and consuming significant chip area and power.
Innovation Solution
Implementing an effective address-based load-store unit that uses an effective address directory (EAD) and effective real table (ERT) to track and translate effective addresses, reducing the need for real address translation and minimizing chip area and power consumption by policing against effective address aliasing within the OoO window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If real address translation is performed for every load instruction in out-of-order execution, then address translation accuracy is improved, but chip area and power consumption increase significantly
Solution Approach 1:
The patent extracts the address translation function from the load-store unit and implements it separately in the instruction sequencing unit using an effective-real table. This separation allows the LSU to work with effective addresses only, removing the need for redundant translation hardware in the LSU while maintaining accurate address translation through the dedicated ERT structure.
Solution Approach 2:
The patent introduces an effective-real table (ERT) as an intermediary data structure that maps effective addresses to real addresses. This ERT acts as a mediator between the LSU operating in effective address space and the memory subsystem requiring real addresses, enabling accurate translation without duplicating translation hardware in the LSU.
2Measurement precision
If real address translation is performed for every load instruction, then address translation accuracy is improved, but power consumption increases
Solution Approach 1:
The patent extracts the address translation function from the load-store unit and implements it separately in the instruction sequencing unit using an effective-real table. This separation allows the LSU to work with effective addresses only, removing the need for redundant translation hardware in the LSU while maintaining accurate address translation through the dedicated ERT structure.
Solution Approach 2:
The instruction sequencing unit performs address translation proactively before instructions reach the LSU, so the LSU receives already-translated real addresses or effective address mappings. This self-service approach eliminates the need for the LSU to perform translation operations, reducing its power consumption while maintaining translation accuracy.
3Productivity
If younger load instructions are executed before older store instructions in out-of-order execution, then instruction throughput is improved, but pipeline flushes occur due to hazards
Solution Approach 1:
The patent implements preliminary hazard detection by comparing effective addresses of load instructions against store instructions in the out-of-order window before execution. This preliminary action identifies potential load-hit-store and load-hit-load hazards early, allowing the system to prevent pipeline flushes while maintaining out-of-order execution throughput.
Solution Approach 2:
The patent implements feedback mechanisms that monitor effective address usage across the out-of-order window and provide hazard information back to the instruction sequencing unit. This feedback allows the system to detect and handle hazards without flushing the pipeline, maintaining both throughput and reliability.
Data Source
AI summary
Technical solutions are described for executing one or more out-of-order instructions by a processing unit. An example method includes executing, by a load-store unit (LSU), instructions from an out-of-order (OoO) window. The OoO execution includes determining an effective address being used by a load instruction from the OoO window. Further, the execution includes determining presence of the effective address in an effective address directory (EAD) by identifying an EAD entry in the EAD, the EAD entry maps the effective address with an index of a corresponding effective-real table (ERT) entry from an effective-real table (ERT). In response to the effective address being present in the EAD, the execution includes accessing the corresponding ERT entry of the effective address of the load instruction, the corresponding ERT entry including a real address for the effective address, and issuing the load instruction using the real address from the corresponding ERT entry.