Early Buried Power Rail Layout Without Backside Alignment
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Solution Overview
Problem
Existing CMOS integrated circuit technologies face challenges in forming buried power rails and backside power distribution networks, requiring complex processes like substrate thinning and backside lithographic alignment, which are difficult and risky.
Innovation Solution
The implementation of an early buried power rail (BPR) and backside power distribution network (BSPDN) scheme that forms power distribution networks with buried power rails, power wires, and vias before device formation, allowing for thicker, lower-conductivity wires and reducing routing complexity by connecting to back-end-of-line interconnects without wafer flipping or fine backside lithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If substrate thinning and backside lithographic alignment are used to form buried power rails and backside power distribution networks, then power distribution functionality is achieved, but manufacturing complexity and process difficulty increase significantly
Solution Approach 1:
The patent applies preliminary action by forming the buried power rails and backside power distribution networks at an early stage in the fabrication process, before substrate thinning and backside processing. The power rails are created using standard frontside lithography and deposition processes, then encapsulated in dielectric layers before the substrate is thinned. This eliminates the need for complex backside lithographic alignment and reduces manufacturing complexity while maintaining power distribution functionality.
2Reliability
If substrate thinning is performed to access the backside for power rail formation, then backside power distribution is enabled, but process risk and difficulty increase
Solution Approach 1:
The patent performs the power rail formation action in advance, before substrate thinning. The buried power rails are formed, connected to power wires, and encapsulated in dielectric layers while the substrate is still at its original thickness. This preliminary formation eliminates the risks associated with backside processing and makes the manufacturing process easier while still enabling backside power distribution.
3Reliability
If thin wires with high conductivity material are used, then resistance is reduced, but wire thickness is limited by process constraints
Solution Approach 1:
The patent changes the parameter of wire thickness by enabling thicker power wires through the early formation approach. Since the power wires are formed before substrate thinning and backside processing, they can be made thicker without being constrained by the limited space and alignment precision required for backside lithography. This parameter change allows using thicker wires with lower conductivity materials while still achieving acceptable resistance levels.
Data Source
AI summary
A semiconductor structure includes a power distribution network including a first buried power rail, a power wire, and a first buried via electrically interconnecting the first buried power rail and the power wire. Each of the first buried power rail, the power wire, and the first buried via have a liner on a corresponding bottom surface thereof and sidewalls thereof. The structure also includes a dielectric layer outward of the power distribution network; a first field effect transistor outward of the dielectric layer; a first via trench contact electrically interconnecting a source/drain region of the transistor to the first buried power rail; a first outer wire outward of the first field effect transistor; and an electrical path electrically interconnecting the first outer wire with the power wire.