Early Call Fetch Circuitry for Reducing Instruction Cache Misses
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Solution Overview
Problem
The performance of out-of-order processors is sensitive to the smooth supply of instructions, with instruction cache misses and mispredictions by branch predictors leading to inefficiencies in fetching and executing speculative code, resulting in performance bottlenecks.
Innovation Solution
Implementing an Early CAll instruction Fetch (ECAF) circuit that uses discarded branch predictor run-ahead to prefetch direct call targets, leveraging hardware or ISA modifications to identify and fetch call targets early in the pipeline, reducing cache misses and improving instruction supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If branch predictor run-ahead is used to fetch speculative code, then instruction supply is improved, but cache misses increase leading to performance bottlenecks
Solution Approach 1:
The patent applies preliminary action by detecting call instructions and prefetching their target addresses before they are actually needed for execution. The ECAF circuit identifies call instructions in the instruction stream and pre-fetches the target code into the instruction cache, so that when the call is executed, the target code is already available, avoiding cache misses and maintaining high instruction supply.
2Reliability
If early fetch of call instructions is implemented, then cache misses are reduced, but hardware complexity increases
Solution Approach 1:
The patent extracts the call instruction detection and target address calculation functionality from the main processor pipeline and implements it as a separate ECAF circuit. This dedicated circuit monitors the instruction stream, identifies call instructions by their opcode, calculates target addresses using the branch target buffer, and issues prefetch requests independently, adding minimal hardware while significantly improving cache hit rate.
3Productivity
If discarded branch predictor run-ahead is utilized, then instruction fetch efficiency is improved, but loss of information from discarded speculative code is converted to useful prefetch data
Solution Approach 1:
The patent converts the harmful effect of discarded speculative code into a beneficial resource. The ECAF circuit uses the same run-ahead mechanism that was previously discarded to detect call instructions and prefetch their targets. By repurposing the discarded branch predictor information, the system improves instruction fetch efficiency without requiring additional hardware resources.
Data Source
AI summary
Techniques for early fetch of one or more call instructions are described. In certain examples, a hardware processor comprises a memory; an instruction fetch circuit to fetch an instruction from the memory for decode; a decoder circuit to decode the fetched instruction; and an early “call instruction” fetch circuit to determine that the instruction is a direct call, and in response to the instruction being the direct call, determine a target address for the direct call, and cause the target address to be sent to the instruction fetch circuit for a fetch of one or more instructions at the target address. In certain examples, the early call instruction fetch circuit is to determine that the instruction is the direct call based on an opcode of the fetched instruction.