Early Completion Transmission in Serial Electronic Device Systems
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Solution Overview
Problem
In computing systems with serially connected electronic devices, latency issues arise when high-speed endpoint devices communicate with a host, leading to slow communication speeds due to switch latencies between devices.
Innovation Solution
A computing system design that includes a host, a first electronic device with a memory and an accelerator, and a second electronic device with a DMA engine, where the DMA engine transmits data and completion information based on commands from the host, and the accelerator executes calculations, allowing early transmission of completion signals through a completion queue buffer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If electronic devices are connected serially to enable communication between host and endpoint devices, then device interconnection and communication capability are improved, but communication speed deteriorates due to latency introduced by intermediate devices
Solution Approach 1:
The completion queue buffer pre-allocates storage space for completion information before it is needed. The DMA engine writes completion information to this pre-allocated buffer immediately upon command completion, allowing the host to read completion information without waiting for data transmission to finish, thus reducing communication latency while maintaining serial connection architecture
Solution Approach 2:
The completion queue buffer acts as an intermediary between the DMA engine and the host. It decouples the completion notification from the data transmission process, allowing the host to receive completion information independently of the actual data transfer status, thereby improving communication speed without sacrificing the versatility of serial device interconnection
2Reliability
If data transmission through intermediate electronic devices is performed sequentially (data first, then completion information), then data integrity is ensured, but communication latency increases
Solution Approach 1:
The transmission process is segmented into two independent channels: data transmission through the serial device chain and completion information transmission through the completion queue buffer. This segmentation allows completion information to be transmitted and stored independently of data transmission timing, reducing latency while maintaining data integrity through separate but coordinated pathways
Solution Approach 2:
The completion queue buffer is pre-allocated and ready to receive completion information immediately when the DMA engine completes a command. This preliminary preparation eliminates the need to wait for data transmission to finish before storing completion information, significantly reducing communication latency while ensuring data integrity through proper buffer management
Data Source
AI summary
A computing system includes a host, a first electronic device including a memory and an accelerator, and a second electronic device including a direct memory access (DMA) engine. Based on a command transmitted from the host through the first electronic device, the DMA engine transmits data and completion information of the command to the first electronic device. The memory includes a data buffer storing the data and a completion queue buffer storing the completion information. The accelerator executes a calculation on the data. The DMA engine transmits the data to the first electronic device and then transmits the completion information to the first electronic device.