Early Coverage Discard Logic for Tile-Based Graphics Rendering
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Solution Overview
Problem
Conventional approaches to hidden surface removal (HSR) and pixel shading in graphics processing units (GPUs) fail to provide sufficient performance and energy savings, especially in complex computational environments with increasing demands.
Innovation Solution
The implementation of an early coverage discard (ECD) method in a tile-based graphics rendering pipeline, which uses a coverage block information (CBI) logic section with a FIFO buffer to identify and discard redundant coverage, reducing pixel shader work by comparing coverage blocks against a tile coverage-to-primitive map (TCPM) and performing depth testing before pixel shading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional hidden surface removal approaches are used, then basic rendering functionality is maintained, but pixel shader work and energy consumption remain high
Solution Approach 1:
The patent performs depth testing and coverage block comparison operations before pixels enter the pixel shader stage. By using an early coverage discard (ECD) logic section that compares coverage blocks against a tile coverage-to-primitive map (TCPM), the system identifies and discards redundant coverage early in the pipeline, preventing unnecessary pixel shader executions and reducing overall energy consumption while maintaining rendering correctness
Solution Approach 2:
The patent extracts the coverage discarding function from the conventional rendering pipeline by introducing a dedicated ECD logic section. This separate unit specifically handles the comparison of coverage blocks with TCPM data and performs depth testing, isolating the redundant coverage identification and removal process from the main pixel shading path, thereby reducing pixel shader workload without affecting other rendering operations
2Productivity
If redundant coverage is not discarded, then processing simplicity is maintained, but unnecessary pixel shading computations increase
Solution Approach 1:
The patent segments the rendering pipeline into distinct functional sections: rasterization, early coverage discard (ECD), and pixel shading. The ECD section is further divided into coverage block comparison logic and depth testing logic. This segmentation allows each component to perform its specific function efficiently, with the ECD section handling coverage validation before pixels reach the computationally intensive pixel shader stage, thereby improving processing efficiency without requiring complete pipeline redesign
Solution Approach 2:
The patent introduces a tile coverage-to-primitive map (TCPM) as an intermediary data structure between rasterization and pixel shading. The TCPM stores depth information and coverage data that the ECD logic section uses to determine whether coverage blocks are redundant. This intermediary structure enables efficient comparison and discarding operations without requiring complex real-time calculations, balancing the added pipeline complexity with significant reductions in unnecessary pixel shading computations
Data Source
AI summary
A computer-implemented redundant-coverage discard method and apparatus for reducing pixel shader work in a tile-based graphics rendering pipeline is disclosed. A coverage block information (CBI) FIFO buffer is disposed within an early coverage discard (ECD) logic section. The FIFO buffer receives and buffers coverage blocks in FIFO order. At least one coverage block that matches the block position within the TCPM is updated. The TCPM stores per-pixel primitive coverage information. The FIFO buffer buffers a moving window of the coverage blocks. Incoming primitive information associated with the coverage blocks is compared with the per-pixel primitive coverage information stored in the tile coverage-primitive map (TCPM) table at the corresponding positions for the live coverages only. Any preceding overlapping coverage within the moving window of the coverage blocks is rejected. An alternate embodiment uses a doubly linked-list rather than a FIFO buffer.