Early Fence Operation Reducing Memory Synchronization Latency

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Solution Overview

Problem

Traditional memory fence operations incur high latency due to the need for all sub-operations to complete before the thread can proceed, which hinders efficient inter-thread communication and synchronization in multi-threaded environments.

Innovation Solution

Implementing an early fence operation that initiates some sub-operations ahead of time, followed by a resolving fence operation to complete the remaining sub-operations, thereby reducing the overall latency experienced by the thread.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a traditional memory fence operation is executed to ensure proper synchronization, then thread synchronization reliability is improved, but thread execution speed deteriorates due to high latency

Engineering Contradiction:
Improvethread synchronization reliabilityVSAvoidthread execution speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies preliminary action by executing an early fence operation before the actual fence point to initiate sub-operations in advance. This early fence operation starts making data globally visible before the thread reaches the official fence instruction, thereby reducing the latency impact on thread execution speed while maintaining synchronization reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the traditional single fence operation into two distinct operations: an early fence operation that initiates sub-operations ahead of time, and a resolving fence operation that completes the remaining sub-operations. This segmentation allows the thread to continue executing other instructions while fence sub-operations are being performed, reducing overall latency.

Inventive Principle:
Principle #1Segmentation

2Reliability

If all fence sub-operations are completed before thread proceeds, then synchronization correctness is improved, but productivity deteriorates due to thread stalling

Engineering Contradiction:
Improvesynchronization correctnessVSAvoidthread productivity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The early fence operation performs preliminary actions by initiating fence sub-operations before the thread needs to stall. This allows the thread to maintain productivity by executing other instructions while the synchronization work is being prepared in the background, without compromising synchronization correctness.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent enables continuity of useful action by allowing the thread to continue executing productive instructions between the early fence operation and the resolving fence operation. The fence sub-operations proceed in the background without interrupting the thread's productive work, thereby maintaining both correctness and productivity.

Inventive Principle:
Principle #20Continuity of useful action

3Speed

If early fence operation is executed to reduce latency, then thread execution speed is improved, but device complexity increases due to additional fence operations

Engineering Contradiction:
Improvethread execution speedVSAvoidfence operation complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The early fence operation and resolving fence operation together serve the universal function of complete synchronization. The early fence initiates sub-operations and the resolving fence completes them, creating a multi-functional fence mechanism that reduces latency while managing complexity through a systematic two-stage approach that can be uniformly applied.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10990453B2Improving latency by performing early synchronization operations in between sets of program operations of a thread
Publication Date: 2021.04.27 ADVANCED MICRO DEVICES INC
  • US10990453B2 patent drawing
  • US10990453B2 patent drawing
  • US10990453B2 patent drawing

AI summary

A memory fence or other similar operation is executed with reduced latency. An early fence operation is executed and acts as a hint to the processor executing the thread that executes the fence. This hint causes the processor to begin performing sub-operations for the fence earlier than if no such hint were executed. Examples of sub-operations for the fence include operations to make data written to by writes prior to the fence operation available to other threads. A resolving fence, which occurs after the early fence, performs the remaining sub-operations for the fence. By triggering some or all of the sub-operations for a memory fence that will occur in the future, the early fence operation reduces the amount of latency associated with that memory fence operation.