Early Predicate Lookup for Vector Lane Masking

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Solution Overview

Problem

In data processing pipelines, predicated vector instructions often result in unnecessary micro-operations being issued due to late predicate value lookups, leading to resource occupation and performance delays, especially when loop unrolling is used, as all lanes may be disabled, necessitating a more efficient method to determine which micro-operations to execute.

Innovation Solution

Implementing an early predicate lookup mechanism at the front end stage of the processing pipeline, utilizing predicate tracking information stored in a separate buffer, which summarizes the predicate value to determine whether lanes are disabled, allowing for the adaptation of micro-operations issued to the execute stage, thereby reducing unnecessary micro-operations and improving resource utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If predicate lookup is performed at the execute stage, then the predicate value is accurately determined, but unnecessary micro-operations are issued and resources are occupied

Engineering Contradiction:
Improvepredicate value determination accuracyVSAvoidpipeline efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent performs predicate lookup at the front end stage before micro-operation issuance, rather than at the execute stage. This preliminary action allows the system to determine which lanes are disabled beforehand, preventing unnecessary micro-operations from being issued to the execute stage, thereby improving pipeline efficiency while maintaining accurate predicate value determination

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the predicate lookup operation from the execute stage and moves it to the front end stage. This separation allows the front end to filter out disabled lanes before micro-operation issuance, reducing the workload at the execute stage and improving overall pipeline productivity without sacrificing accuracy

Inventive Principle:
Principle #2Taking out (Extraction)

2Adaptability or versatility

If separate micro-operations are issued for each lane, then lane-specific control is achieved, but code size increases and performance decreases

Engineering Contradiction:
Improvelane-specific control capabilityVSAvoidprocessing performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent issues micro-operations for only the enabled lanes rather than all lanes. By performing predicate lookup early and identifying which lanes are disabled, the system takes partial action (issuing micro-operations only where needed) rather than excessive action (issuing for all lanes), improving performance while maintaining lane-specific control for enabled lanes

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent segments the micro-operation issuance process by lane enablement status. Through early predicate lookup, the system divides lanes into enabled and disabled groups, issuing micro-operations only for enabled lanes. This segmentation reduces the total number of micro-operations while preserving the ability to control each lane individually when needed

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10628157B2Early predicate look-up
Publication Date: 2020.04.21 ARM LTD
  • US10628157B2 patent drawing
  • US10628157B2 patent drawing
  • US10628157B2 patent drawing

AI summary

A processing pipeline has at least one front end stage for issuing micro-operations for execution in response to program instructions, and an execute stage for performing data processing in response to the micro-operations. At least one predicate register stores at least one predicate value. In response to a predicated vector instruction for triggering execution of two or more lanes of processing, the at least one front end stage issues at least one micro-operation to control the execute stage to mask an effect of a lane of processing indicated as disabled by a target predicate value. One of the front end stages may perform an early predicate lookup of the target predicate value to vary in dependence on the early predicate lookup, which micro-operations are issued to the execute store for a predicated vector instruction.