Early Update Write Pointer Latency Reduction
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Solution Overview
Problem
Asynchronous storage circuits used for propagating data across clock boundaries face high latency due to the need for complex write pointer synchronization circuitry, especially at high frequencies, which is costly and inefficient.
Innovation Solution
The introduction of early update circuitry that alters the write pointer indication ahead of the write operation by a number of clock cycles dependent on the clock speed difference between domains and the synchronization cycles, decoupling the incrementing of the write pointer from the data writing process to reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write pointer synchronisation circuitry is used to reduce metastability probability, then reliability is improved, but device complexity and latency increase
Solution Approach 1:
The patent applies preliminary action by incrementing the write pointer one or more clock cycles before the actual write operation occurs. This advance pointer increment allows the pointer value to be propagated through synchronisation circuitry ahead of time, reducing metastability issues when the pointer is sampled by read circuitry in a different clock domain, while avoiding the need for complex multi-stage synchronisation of the pointer itself
Solution Approach 2:
The patent segments the write pointer into two independent components: the write pointer indication (WPI) that is incremented early and propagated to read circuitry, and the actual write data that is written later. This segmentation allows the pointer information to be synchronised independently from the data, simplifying the synchronisation circuitry requirements while maintaining reliability
2Reliability
If write pointer is incremented at the same time as data is written, then data validity is ensured, but latency increases due to synchronisation requirements
Solution Approach 1:
The patent performs preliminary action by incrementing the write pointer indication before the write operation completes. Specifically, the WPI is incremented one or more clock cycles early, allowing this pointer information to flow through the storage structure and be captured by read circuitry before the actual data write completes, thereby reducing the latency penalty of pointer synchronisation
Solution Approach 2:
The patent maintains continuity of useful action by ensuring that the write pointer indication is continuously updated and propagated through the storage structure ahead of the actual data writes. This continuous early updating of the pointer allows read circuitry to continuously know when data is available, eliminating idle waiting time while maintaining data validity guarantees
Data Source
AI summary
A storage circuit and method are provided for propagating data values across a clock boundary between a first clock domain and a second clock domain. A storage structure is provided with at least one entry, and write circuitry performs write operations in the first clock domain, where each write operation writes a data value into an entry of the storage structure identified by a write pointer. The write circuitry alters the write pointer between each write operation. Write pointer synchronization circuitry then receives the write pointer and synchronizes the write pointer indication to the second clock domain over a predetermined number of clock cycles of the second clock domain. Read circuitry performs read operations in the second clock domain, with each read operation reading a data value from an entry of the storage structure identified by a read pointer. However, for a read operation to be performed, it is necessary that the synchronized write pointer indication indicates that there is a data value written into the storage structure that is available to be read. Early update circuitry is configured, for a write operation, to alter the write pointer indication provided to the write pointer synchronization circuitry a number of clock cycles of the first clock domain before the write operation is performed. That number of clock cycles is chosen dependent on the difference in clock speed between the first clock domain and the second clock domain, and the predetermined number of clock cycles of the second clock domain taken by the write pointer synchronization circuitry to synchronize the write pointer indication to the second clock domain. Such an approach enables at least a part of the latency of the write pointer synchronization circuitry to be hidden, thereby improving performance of the storage circuitry.