EAVB Descriptor Sorting Engine for Low-Latency AV Synchronization
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Solution Overview
Problem
Conventional Ethernet audio and video bridging (EAVB) systems in automobiles face challenges with synchronization, latency, and power consumption, particularly for audio-visual components, due to the use of multiple cable types and the need to comply with IEEE standards like IEEE 1722, IEEE 802.1AS, IEEE 802.1Qav, and IEEE 802.1Qat, which are not adequately addressed by existing solutions.
Innovation Solution
Implementing a hardware-based Ethernet audio and video bridging (EAVB) packet/descriptor sorting system using a descriptor sorting engine (DSE) with a DMA controller, FIFO memories, and TS sorting logic to reorder timestamp-pointer pairs, and an Ethernet media access controller (EMAC) to streamline packet transfer according to the generalized precision time protocol (gPTP), with optional use of a dedicated descriptor ring scanner (DRS) hardware for enhanced synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional Ethernet EAVB systems use multiple cable types and standard Ethernet switches, then system compatibility and ease of manufacture are improved, but synchronization precision and latency are worsened
Solution Approach 1:
The system segments packet processing into distinct hardware components: a descriptor sorting engine separates timestamp extraction and sorting functions from the main Ethernet switch, while FIFO buffers segment different audio/video streams into dedicated channels. This segmentation enables precise timestamp-based sorting without requiring modification of the entire Ethernet infrastructure, thus maintaining compatibility while improving synchronization precision.
Solution Approach 2:
The patent introduces an intermediary descriptor sorting engine between the Ethernet switch and the audio/video processing components. This intermediary hardware component receives packets from the standard Ethernet switch, extracts timestamps, sorts packets based on timestamps using FIFO buffers, and outputs sorted packets to the destination. This intermediary approach enables precise synchronization without modifying the existing Ethernet infrastructure.
2Manufacturing precision
If hardware-based packet sorting is implemented, then synchronization precision is improved, but device complexity is worsened
Solution Approach 1:
The patent extracts the complex timestamp sorting functionality from the main Ethernet switch into a separate, dedicated descriptor sorting engine. This extracted component contains only the necessary functions for timestamp extraction, FIFO buffer management, and packet sorting, while the main Ethernet switch retains its standard functionality. This extraction reduces the complexity burden on the primary system while achieving precise synchronization.
Solution Approach 2:
The descriptor sorting engine is designed with multi-functionality to handle various audio and video streams simultaneously through multiple FIFO buffers, process different packet types, and interface with standard Ethernet switches. This universal design allows a single hardware component to perform multiple sorting operations for different media types, reducing overall system complexity compared to having separate sorting mechanisms for each stream type.
3Manufacturing precision
If timestamp-based packet sorting is performed, then audio-video synchronization is improved, but processing workload is worsened
Solution Approach 1:
The patent replaces software-based packet sorting with a hardware-based descriptor sorting engine that performs timestamp extraction and packet sorting through dedicated electronic circuits and FIFO buffers. This mechanical/electronic substitution eliminates the need for software processing of each packet timestamp, significantly reducing the CPU processing workload while maintaining precise audio-video synchronization through hardware-level timestamp comparison and sorting operations.
Data Source
AI summary
Various embodiments include an automobile network device that includes a descriptor sorting engine (DSE). The DSE may include a direct memory access (DMA) controller, a memory organized by channel clusters that each include a plurality of first-in first-out (FIFO) memories, a timer, and a time stamp (TS) sorting logic component. The DMA controller may be configured to pull timestamp-pointer pairs from packet descriptors stored in an unsorted descriptor ring memory, store the timestamp-pointer pairs in the FIFO memories, trigger the TS sorting logic component to reorder the timestamp-pointer pairs in the FIFO memories so that they are sorted in ascending order, use the sorted timestamp-pointer pairs in the FIFO memories to read the packet descriptors stored in an unsorted descriptor ring memory, and store the packet descriptors in a sorted descriptor ring memory.