EBeam Inspection Method for Voltage Contrast Defect Detection
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Solution Overview
Problem
Current defect inspection methods in semiconductor manufacturing, particularly for identifying voltage contrast (VC) defects, face challenges in high throughput and accuracy when dealing with defects involving few pixels or within one image, especially for logic circuits and memory devices, where controlling accumulated charges is difficult and image resolution is low.
Innovation Solution
A method utilizing a charged particle beam, such as an electron beam from a scanning electron microscope, to scan samples, align patterns with design layout information, and determine abnormalities by comparing grey levels, allowing for the identification of defects at the pixel level within a single image, even for logic circuits, using a threshold grey level and aligning patterns to identify voltage contrast defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large beam current is used for VC defect inspection, then inspection throughput is improved, but image resolution deteriorates due to aberration
Solution Approach 1:
The inspection process is divided into two distinct stages: first, low-magnification inspection using large beam current for high throughput VC defect detection; second, high-magnification verification using small beam current for fine defect identification. This segmentation allows each stage to operate under optimal conditions without compromise.
Solution Approach 2:
The low-magnification inspection using large beam current is performed as a preliminary action to quickly identify potential VC defects and their approximate locations. This preliminary inspection guides the subsequent high-magnification verification, avoiding the need to perform high-resolution inspection on the entire wafer surface.
2Reliability
If three images from three dice are used for VC defect inspection, then defect identification capability is improved, but inspection time increases
Solution Approach 1:
Instead of requiring three full images from three dice for every inspection, the method performs partial inspection by first examining one image at low magnification to identify potential VC defects. Only suspicious regions are then verified using additional images or high-magnification inspection, reducing the total number of images that need to be processed.
Solution Approach 2:
The inspection quality is made local rather than uniform: low-magnification inspection is applied to the entire wafer surface for quick VC defect screening, while high-magnification verification is applied only to specific suspicious regions. This local quality approach ensures high reliability where needed while minimizing overall inspection time.
3Measurement precision
If image resolution is increased to identify fine defects, then defect detection accuracy is improved, but throughput decreases
Solution Approach 1:
The inspection process is divided into two distinct stages: first, low-magnification inspection using large beam current for high throughput VC defect detection; second, high-magnification verification using small beam current for fine defect identification. This segmentation allows each stage to operate under optimal conditions without compromise.
Solution Approach 2:
The low-magnification inspection using large beam current is performed as a preliminary action to quickly identify potential VC defects and their approximate locations. This preliminary inspection guides the subsequent high-magnification verification, avoiding the need to perform high-resolution inspection on the entire wafer surface.
4Reliability
If review SEM is used to identify defects in one pattern, then defect detection capability is improved, but throughput cannot match ebeam inspection tool
Solution Approach 1:
The inspection process is divided into two distinct stages: first, low-magnification inspection using large beam current for high throughput VC defect detection; second, high-magnification verification using small beam current for fine defect identification. This segmentation allows each stage to operate under optimal conditions without compromise.
Solution Approach 2:
The method merges the advantages of VC defect inspection (high throughput using large beam current) with the advantages of review SEM (high magnification for fine defect identification) into a single integrated process. The low-magnification VC inspection and high-magnification verification are combined in sequence, achieving both high throughput and high defect detection capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-throughput defect inspection capable of identifying finer defects, including those at the pixel level, and monitors process uniformity, improving upon existing methods by allowing for defect detection in one image and enhancing the yield of defect identification for both logic and memory devices.
Implementation Method 1
abnormal charges, either positive or negative, will be accumulated on surface of an electronic device to generate VC(voltage contrast) thereon when the ebeam scans, so it affects the secondary electrons emanated from the surface of the electronic device into the detector
Implementation Method 2
abnormal charges, either positive or negative, will be accumulated on surface of an electronic device to generate VC(voltage contrast) thereon when the ebeam scans
Data Source
AI summary
An image is obtained by using a charged particle beam, and a design layout information is generated to select patterns of interest. Grey levels among patterns can be compared with each other to identify abnormal, or grey levels within one pattern can be compared to a determined threshold grey level to identify abnormal.