E-beam Writing Jog Reduction for Mask Making Cycle Time
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing mask making cycle time and cost due to the complexity of creating photomasks for advanced IC technologies with smaller feature sizes, where e-beam writing time is prolonged and the number of jog features increases, leading to longer fabrication times and higher costs.
Innovation Solution
A method is introduced that includes a jog reduction process in the IC design layout after optical proximity correction (OPC) but before fracturing, which identifies and adjusts candidate jog features using specific rules and a lookup table to minimize their impact on the contour and imaging, thereby reducing the number of jog features and simplifying e-beam writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If optical proximity correction (OPC) is applied to improve imaging effect, then imaging quality is improved, but the number of jog features increases and e-beam writing time is prolonged
Solution Approach 1:
The patent extracts and removes jog features from the IC design layout after OPC processing. By identifying jog features that meet specific criteria (length, position, orientation) and removing them through targeted adjustments, the method eliminates the harmful side effect of OPC while preserving the improved imaging quality.
Solution Approach 2:
The patent performs preliminary jog feature identification and removal before the e-beam writing process. By pre-processing the layout to eliminate jog features that would increase writing time, the method prepares an optimized layout that maintains OPC imaging benefits while reducing subsequent writing time.
2Manufacturing precision
If the IC pattern is modified with more jogs for optical proximity correction, then imaging effect is improved, but mask making cycle time is prolonged
Solution Approach 1:
The patent extracts and removes unnecessary jog features from the IC design layout. By identifying jog features that meet specific criteria and removing them through targeted adjustments, the method eliminates the harmful side effect of OPC while preserving the improved imaging quality, thereby reducing mask making cycle time.
Solution Approach 2:
The patent changes the parameters of jog features by applying specific removal criteria (length thresholds, position requirements, orientation constraints). By modifying the layout parameters to eliminate excessive jogs while maintaining essential imaging corrections, the method improves both imaging effect and mask making efficiency.
3Manufacturing precision
If the IC pattern is modified with more jogs for optical proximity correction, then imaging effect is improved, but mask making cost is higher
Solution Approach 1:
The patent extracts and removes unnecessary jog features from the IC design layout. By identifying jog features that meet specific criteria and removing them through targeted adjustments, the method eliminates the harmful side effect of OPC while preserving the improved imaging quality, thereby reducing mask making cost.
Solution Approach 2:
The patent changes the parameters of jog features by applying specific removal criteria (length thresholds, position requirements, orientation constraints). By modifying the layout parameters to eliminate excessive jogs while maintaining essential imaging corrections, the method improves both imaging effect and manufacturing efficiency, reducing overall cost.
Data Source
AI summary
The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced.